From fe95e24656436c09c185cd6801c873524c10d076 Mon Sep 17 00:00:00 2001 From: Junliang Yan Date: Thu, 28 Jan 2021 16:01:54 -0500 Subject: [PATCH] s390x: implement a few binary op variants Change-Id: I7f1d5e39033957410a8f3601100c7b7c5839271f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2657475 Reviewed-by: Milad Fa Commit-Queue: Junliang Yan Cr-Commit-Position: refs/heads/master@{#72414} --- src/codegen/s390/macro-assembler-s390.cc | 122 +++++++++++++++++++++++ src/codegen/s390/macro-assembler-s390.h | 14 +++ 2 files changed, 136 insertions(+) diff --git a/src/codegen/s390/macro-assembler-s390.cc b/src/codegen/s390/macro-assembler-s390.cc index 4a44d8ccc5..160f8b79fb 100644 --- a/src/codegen/s390/macro-assembler-s390.cc +++ b/src/codegen/s390/macro-assembler-s390.cc @@ -2652,6 +2652,10 @@ void TurboAssembler::AddS64(Register dst, const Operand& opnd) { agfi(dst, opnd); } +void TurboAssembler::AddS32(Register dst, Register src, int32_t opnd) { + AddS32(dst, src, Operand(opnd)); +} + // Add 32-bit (Register dst = Register src + Immediate opnd) void TurboAssembler::AddS32(Register dst, Register src, const Operand& opnd) { if (dst != src) { @@ -2664,6 +2668,10 @@ void TurboAssembler::AddS32(Register dst, Register src, const Operand& opnd) { AddS32(dst, opnd); } +void TurboAssembler::AddS64(Register dst, Register src, int32_t opnd) { + AddS64(dst, src, Operand(opnd)); +} + // Add Pointer Size (Register dst = Register src + Immediate opnd) void TurboAssembler::AddS64(Register dst, Register src, const Operand& opnd) { if (dst != src) { @@ -2823,11 +2831,19 @@ void TurboAssembler::SubS64(Register dst, const Operand& imm) { AddS64(dst, Operand(-(imm.immediate()))); } +void TurboAssembler::SubS32(Register dst, Register src, int32_t imm) { + SubS32(dst, src, Operand(imm)); +} + // Subtract 32-bit (Register dst = Register src - Immediate opnd) void TurboAssembler::SubS32(Register dst, Register src, const Operand& imm) { AddS32(dst, src, Operand(-(imm.immediate()))); } +void TurboAssembler::SubS64(Register dst, Register src, int32_t imm) { + SubS64(dst, src, Operand(imm)); +} + // Subtract Pointer Sized (Register dst = Register src - Immediate opnd) void TurboAssembler::SubS64(Register dst, Register src, const Operand& imm) { AddS64(dst, src, Operand(-(imm.immediate()))); @@ -3964,6 +3980,112 @@ void TurboAssembler::StoreV128(Simd128Register src, const MemOperand& mem, } } +void TurboAssembler::AddF32(DoubleRegister dst, DoubleRegister lhs, + DoubleRegister rhs) { + if (dst == lhs) { + aebr(dst, rhs); + } else if (dst == rhs) { + aebr(dst, lhs); + } else { + ler(dst, lhs); + aebr(dst, rhs); + } +} + +void TurboAssembler::SubF32(DoubleRegister dst, DoubleRegister lhs, + DoubleRegister rhs) { + if (dst == lhs) { + sebr(dst, rhs); + } else if (dst == rhs) { + sebr(dst, lhs); + lcebr(dst, dst); + } else { + ler(dst, lhs); + sebr(dst, rhs); + } +} + +void TurboAssembler::MulF32(DoubleRegister dst, DoubleRegister lhs, + DoubleRegister rhs) { + if (dst == lhs) { + meebr(dst, rhs); + } else if (dst == rhs) { + meebr(dst, lhs); + } else { + ler(dst, lhs); + meebr(dst, rhs); + } +} + +void TurboAssembler::DivF32(DoubleRegister dst, DoubleRegister lhs, + DoubleRegister rhs) { + if (dst == lhs) { + debr(dst, rhs); + } else if (dst == rhs) { + lay(sp, MemOperand(sp, -kSystemPointerSize)); + StoreF32(dst, MemOperand(sp)); + ler(dst, lhs); + deb(dst, MemOperand(sp)); + la(sp, MemOperand(sp, kSystemPointerSize)); + } else { + ler(dst, lhs); + debr(dst, rhs); + } +} + +void TurboAssembler::AddF64(DoubleRegister dst, DoubleRegister lhs, + DoubleRegister rhs) { + if (dst == lhs) { + adbr(dst, rhs); + } else if (dst == rhs) { + adbr(dst, lhs); + } else { + ldr(dst, lhs); + adbr(dst, rhs); + } +} + +void TurboAssembler::SubF64(DoubleRegister dst, DoubleRegister lhs, + DoubleRegister rhs) { + if (dst == lhs) { + sdbr(dst, rhs); + } else if (dst == rhs) { + sdbr(dst, lhs); + lcdbr(dst, dst); + } else { + ldr(dst, lhs); + sdbr(dst, rhs); + } +} + +void TurboAssembler::MulF64(DoubleRegister dst, DoubleRegister lhs, + DoubleRegister rhs) { + if (dst == lhs) { + mdbr(dst, rhs); + } else if (dst == rhs) { + mdbr(dst, lhs); + } else { + ldr(dst, lhs); + mdbr(dst, rhs); + } +} + +void TurboAssembler::DivF64(DoubleRegister dst, DoubleRegister lhs, + DoubleRegister rhs) { + if (dst == lhs) { + ddbr(dst, rhs); + } else if (dst == rhs) { + lay(sp, MemOperand(sp, -kSystemPointerSize)); + StoreF64(dst, MemOperand(sp)); + ldr(dst, lhs); + ddb(dst, MemOperand(sp)); + la(sp, MemOperand(sp, kSystemPointerSize)); + } else { + ldr(dst, lhs); + ddbr(dst, rhs); + } +} + void TurboAssembler::AddFloat32(DoubleRegister dst, const MemOperand& opnd, DoubleRegister scratch) { if (is_uint12(opnd.offset())) { diff --git a/src/codegen/s390/macro-assembler-s390.h b/src/codegen/s390/macro-assembler-s390.h index fb5b91d3c1..a08c5bdf95 100644 --- a/src/codegen/s390/macro-assembler-s390.h +++ b/src/codegen/s390/macro-assembler-s390.h @@ -184,6 +184,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { void AddS64(Register dst, const Operand& imm); void AddS32(Register dst, Register src, const Operand& imm); void AddS64(Register dst, Register src, const Operand& imm); + void AddS32(Register dst, Register src, int32_t imm); + void AddS64(Register dst, Register src, int32_t imm); // Add (Register - Register) void AddS32(Register dst, Register src); @@ -215,6 +217,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { void SubS64(Register dst, const Operand& imm); void SubS32(Register dst, Register src, const Operand& imm); void SubS64(Register dst, Register src, const Operand& imm); + void SubS32(Register dst, Register src, int32_t imm); + void SubS64(Register dst, Register src, int32_t imm); // Subtract (Register - Register) void SubS32(Register dst, Register src); @@ -391,6 +395,16 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { void StoreV128LE(Simd128Register src, const MemOperand& mem, Register scratch1, Register scratch2); + void AddF32(DoubleRegister dst, DoubleRegister lhs, DoubleRegister rhs); + void SubF32(DoubleRegister dst, DoubleRegister lhs, DoubleRegister rhs); + void MulF32(DoubleRegister dst, DoubleRegister lhs, DoubleRegister rhs); + void DivF32(DoubleRegister dst, DoubleRegister lhs, DoubleRegister rhs); + + void AddF64(DoubleRegister dst, DoubleRegister lhs, DoubleRegister rhs); + void SubF64(DoubleRegister dst, DoubleRegister lhs, DoubleRegister rhs); + void MulF64(DoubleRegister dst, DoubleRegister lhs, DoubleRegister rhs); + void DivF64(DoubleRegister dst, DoubleRegister lhs, DoubleRegister rhs); + void AddFloat32(DoubleRegister dst, const MemOperand& opnd, DoubleRegister scratch); void AddFloat64(DoubleRegister dst, const MemOperand& opnd,