S390: [wasm-simd] Prototype extended pairwise addition
Bug: v8:11086 Change-Id: Ic59e270282b5b7f3d2f8e8b46586964c69e4447a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2618289 Reviewed-by: Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71991}
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Milad Fa
Commit Bot
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@ -4187,6 +4187,40 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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break;
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}
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#undef ASSEMBLE_SIMD_I32X4_I16X8_EXT_MUL
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#define EXT_ADD_PAIRWISE(lane_size, mul_even, mul_odd) \
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Simd128Register src = i.InputSimd128Register(0); \
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Simd128Register dst = i.OutputSimd128Register(); \
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Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); \
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__ vrepi(kScratchDoubleReg, Operand(1), Condition(lane_size)); \
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__ mul_even(tempFPReg1, src, kScratchDoubleReg, Condition(0), Condition(0), \
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Condition(lane_size)); \
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__ mul_odd(kScratchDoubleReg, src, kScratchDoubleReg, Condition(0), \
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Condition(0), Condition(lane_size)); \
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__ va(dst, tempFPReg1, kScratchDoubleReg, Condition(0), Condition(0), \
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Condition(lane_size + 1));
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case kS390_I32x4ExtAddPairwiseI16x8S: {
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EXT_ADD_PAIRWISE(1, vme, vmo)
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break;
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}
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case kS390_I32x4ExtAddPairwiseI16x8U: {
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Simd128Register src0 = i.InputSimd128Register(0);
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Simd128Register dst = i.OutputSimd128Register();
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__ vx(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg,
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Condition(0), Condition(0), Condition(3));
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__ vsum(dst, src0, kScratchDoubleReg, Condition(0), Condition(0),
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Condition(1));
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break;
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}
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case kS390_I16x8ExtAddPairwiseI8x16S: {
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EXT_ADD_PAIRWISE(0, vme, vmo)
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break;
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}
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case kS390_I16x8ExtAddPairwiseI8x16U: {
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EXT_ADD_PAIRWISE(0, vmle, vmlo)
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break;
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}
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#undef EXT_ADD_PAIRWISE
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case kS390_StoreCompressTagged: {
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CHECK(!instr->HasOutput());
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size_t index = 0;
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@ -294,6 +294,8 @@ namespace compiler {
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V(S390_I32x4ExtMulHighI16x8S) \
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V(S390_I32x4ExtMulLowI16x8U) \
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V(S390_I32x4ExtMulHighI16x8U) \
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V(S390_I32x4ExtAddPairwiseI16x8S) \
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V(S390_I32x4ExtAddPairwiseI16x8U) \
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V(S390_I16x8Splat) \
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V(S390_I16x8ExtractLaneU) \
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V(S390_I16x8ExtractLaneS) \
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@ -333,6 +335,8 @@ namespace compiler {
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V(S390_I16x8ExtMulHighI8x16S) \
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V(S390_I16x8ExtMulLowI8x16U) \
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V(S390_I16x8ExtMulHighI8x16U) \
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V(S390_I16x8ExtAddPairwiseI8x16S) \
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V(S390_I16x8ExtAddPairwiseI8x16U) \
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V(S390_I8x16Splat) \
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V(S390_I8x16ExtractLaneU) \
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V(S390_I8x16ExtractLaneS) \
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@ -240,6 +240,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kS390_I32x4ExtMulHighI16x8S:
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case kS390_I32x4ExtMulLowI16x8U:
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case kS390_I32x4ExtMulHighI16x8U:
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case kS390_I32x4ExtAddPairwiseI16x8S:
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case kS390_I32x4ExtAddPairwiseI16x8U:
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case kS390_I16x8Splat:
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case kS390_I16x8ExtractLaneU:
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case kS390_I16x8ExtractLaneS:
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@ -279,6 +281,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kS390_I16x8ExtMulHighI8x16S:
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case kS390_I16x8ExtMulLowI8x16U:
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case kS390_I16x8ExtMulHighI8x16U:
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case kS390_I16x8ExtAddPairwiseI8x16S:
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case kS390_I16x8ExtAddPairwiseI8x16U:
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case kS390_I8x16Splat:
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case kS390_I8x16ExtractLaneU:
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case kS390_I8x16ExtractLaneS:
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@ -765,7 +765,9 @@ void Simulator::EvalTableInit() {
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V(vs, VS, 0xE7F7) /* type = VRR_C VECTOR SUBTRACT */ \
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V(vml, VML, 0xE7A2) /* type = VRR_C VECTOR MULTIPLY LOW */ \
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V(vme, VME, 0xE7A6) /* type = VRR_C VECTOR MULTIPLY EVEN */ \
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V(vmle, VMLE, 0xE7A4) /* type = VRR_C VECTOR MULTIPLY EVEN LOGICAL */ \
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V(vmo, VMO, 0xE7A7) /* type = VRR_C VECTOR MULTIPLY ODD */ \
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V(vmlo, VMLO, 0xE7A75) /* type = VRR_C VECTOR MULTIPLY LOGICAL ODD */ \
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V(vnc, VNC, 0xE769) /* type = VRR_C VECTOR AND WITH COMPLEMENT */ \
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V(vsum, VSUM, 0xE764) /* type = VRR_C VECTOR SUM ACROSS WORD */ \
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V(vsumg, VSUMG, 0xE765) /* type = VRR_C VECTOR SUM ACROSS DOUBLEWORD */ \
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@ -3220,29 +3222,32 @@ EVALUATE(VML) {
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input_type src1 = get_simd_register_by_lane<input_type>(r3, i); \
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set_simd_register_by_lane<result_type>(r1, k, src0 * src1); \
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}
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#define VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, is_odd) \
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switch (m4) { \
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case 0: { \
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VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, int8_t, int16_t, is_odd) \
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break; \
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} \
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case 1: { \
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VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, int16_t, int32_t, is_odd) \
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break; \
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} \
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case 2: { \
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VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, int32_t, int64_t, is_odd) \
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break; \
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} \
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default: \
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UNREACHABLE(); \
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#define VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, is_odd, sign) \
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switch (m4) { \
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case 0: { \
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VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, sign##int8_t, sign##int16_t, \
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is_odd) \
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break; \
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} \
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case 1: { \
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VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, sign##int16_t, sign##int32_t, \
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is_odd) \
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break; \
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} \
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case 2: { \
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VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, sign##int32_t, sign##int64_t, \
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is_odd) \
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break; \
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} \
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default: \
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UNREACHABLE(); \
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}
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EVALUATE(VME) {
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DCHECK_OPCODE(VME);
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DECODE_VRR_C_INSTRUCTION(r1, r2, r3, m6, m5, m4);
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USE(m5);
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USE(m6);
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VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, false)
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VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, false, )
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return length;
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}
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@ -3251,7 +3256,24 @@ EVALUATE(VMO) {
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DECODE_VRR_C_INSTRUCTION(r1, r2, r3, m6, m5, m4);
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USE(m5);
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USE(m6);
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VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, true)
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VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, true, )
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return length;
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}
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EVALUATE(VMLE) {
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DCHECK_OPCODE(VMLE);
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DECODE_VRR_C_INSTRUCTION(r1, r2, r3, m6, m5, m4);
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USE(m5);
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USE(m6);
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VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, false, u)
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return length;
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}
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EVALUATE(VMLO) {
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DCHECK_OPCODE(VMLO);
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DECODE_VRR_C_INSTRUCTION(r1, r2, r3, m6, m5, m4);
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USE(m5);
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USE(m6);
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VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, true, u)
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return length;
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}
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#undef VECTOR_MULTIPLY_EVEN_ODD
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@ -3295,8 +3317,8 @@ EVALUATE(VSUM) {
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USE(m6);
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USE(m5);
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switch (m4) {
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CASE(1, int8_t, int32_t);
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CASE(2, int16_t, int32_t);
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CASE(0, uint8_t, uint32_t);
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CASE(1, uint16_t, uint32_t);
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default:
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UNREACHABLE();
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}
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@ -3309,8 +3331,8 @@ EVALUATE(VSUMG) {
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USE(m6);
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USE(m5);
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switch (m4) {
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CASE(1, int16_t, int64_t);
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CASE(2, int32_t, int64_t);
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CASE(1, uint16_t, uint64_t);
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CASE(2, uint32_t, uint64_t);
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default:
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UNREACHABLE();
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}
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