From ffb4f2b77fd3abe3d7450312aa3c670776d9502d Mon Sep 17 00:00:00 2001 From: Zhao Jiazhong Date: Thu, 9 Apr 2020 23:33:34 -0400 Subject: [PATCH] [mips][wasm-simd][liftoff] Implement rounding average Port bd04ee08643e8e19314b4ecb335f45344d5f5f00 https://crrev.com/c/2143386 Change-Id: I547c9b5b341abe76d6983a07633129299c32e017 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2143978 Reviewed-by: Zhi An Ng Commit-Queue: Zhao Jiazhong Cr-Commit-Position: refs/heads/master@{#67098} --- .../baseline/mips/liftoff-assembler-mips.h | 18 ++++++++++++++++++ .../baseline/mips64/liftoff-assembler-mips64.h | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/src/wasm/baseline/mips/liftoff-assembler-mips.h b/src/wasm/baseline/mips/liftoff-assembler-mips.h index 10ca44f5c2..e545764351 100644 --- a/src/wasm/baseline/mips/liftoff-assembler-mips.h +++ b/src/wasm/baseline/mips/liftoff-assembler-mips.h @@ -2000,6 +2000,24 @@ void LiftoffAssembler::emit_f64x2_replace_lane(LiftoffRegister dst, bailout(kSimd, "emit_f64x2_replace_lane"); } +void LiftoffAssembler::emit_i8x16_rounding_average_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_rounding_average_u"); +} + +void LiftoffAssembler::emit_i16x8_rounding_average_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i16x8_rounding_average_u"); +} + void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) { TurboAssembler::Ulw(limit_address, MemOperand(limit_address)); TurboAssembler::Branch(ool_code, ule, sp, Operand(limit_address)); diff --git a/src/wasm/baseline/mips64/liftoff-assembler-mips64.h b/src/wasm/baseline/mips64/liftoff-assembler-mips64.h index fd8263fce9..60505bc7b2 100644 --- a/src/wasm/baseline/mips64/liftoff-assembler-mips64.h +++ b/src/wasm/baseline/mips64/liftoff-assembler-mips64.h @@ -1792,6 +1792,24 @@ void LiftoffAssembler::emit_f64x2_replace_lane(LiftoffRegister dst, bailout(kSimd, "emit_f64x2_replace_lane"); } +void LiftoffAssembler::emit_i8x16_rounding_average_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_rounding_average_u"); +} + +void LiftoffAssembler::emit_i16x8_rounding_average_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i16x8_rounding_average_u"); +} + void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) { TurboAssembler::Uld(limit_address, MemOperand(limit_address)); TurboAssembler::Branch(ool_code, ule, sp, Operand(limit_address));