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Author SHA1 Message Date
yangguo@chromium.org
17b33fa1da Handlify code allocation. 
R=mstarzinger@chromium.org

Review URL: https://codereview.chromium.org/235153003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20795 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-16 11:38:56 +00:00
rmcilroy@chromium.org
3eb418df78 Fix fixed-point vcvt_f64_s32 immediate value encoding 
The (32 - fraction_bits) value should be encoded so that the least
significant bit is set to bit 5 and the four next bits to bits 0-3. Fix
the previously incorrect encoding. This bug did not cause behavioral
issues before, since in existing uses of the function the order of the
bits in the immediate value does not matter, as they are all 1.

BUG=3256
LOG=N
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/223623003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20508 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-04 11:12:40 +00:00
m.m.capewell@googlemail.com
6c4178330d ARM: Fix Q register encoding 
Fix Q register encoding for registers other than Q0. Also, fix value in NeonSize
enumeration.

BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/207523005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20163 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-21 13:04:20 +00:00
m.m.capewell@googlemail.com
d6aabbdcc7 ARM: Optimize truncating division and fix sim 
Optimize code generated for DivI Lithium instruction when handling division
where the result is int32. Also, fix the ARM simulator to give the correct
answer for kMinInt / -1.

TEST=Division tests added to test-assembler-arm.cc
BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/102623003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@18445 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-01-02 16:36:21 +00:00
dcarney@chromium.org
e0ecb1a14b cleanup cctest generally and remove ctest::context 
R=svenpanne@chromium.org
BUG=

Review URL: https://codereview.chromium.org/23519010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16831 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-09-19 13:30:47 +00:00
dcarney@chromium.org
baf6add9f0 bulk replace Isolate::Current in tests 
R=svenpanne@chromium.org
BUG=

Review URL: https://codereview.chromium.org/23534067

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16817 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-09-19 09:17:13 +00:00
rodolph.perfetta@gmail.com
6a558d107a ARM: remove the regexp specific literal pool. 
It is replaced by a mov_label_offset(Register, Label*) instruction.

BUG=none
TEST=test/cctest/test-assembler-arm.cc
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/23515007

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16676 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-09-12 10:37:42 +00:00
bmeurer@chromium.org
a4c072ed47 Fix a crash when generating forward jumps to labels at very high assembly offsets 
The first jump to a specific label was marked as jump to absolute
position -4. This value was stored in the assembly as a branch to a
offset (-4 - (instruction offset + 8)). The offset is only 24 bit
long on ARM. Thus instruction offsets higher than 2^23 - 12 would overflow
the offset.

Fix by denoting the first jump to a label by storing the jump
instruction location as the target. This will result in offset of -8,
which of course always fits in the branch instruction.

BUG=2736
TEST=cctest/test-assembler-arm/17
R=bmeurer@chromium.org, svenpanne@chromium.org

Review URL: https://codereview.chromium.org/17116006

Patch from Kimmo Kinnunen <kkinnunen@nvidia.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15997 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-08-01 08:13:08 +00:00
m.m.capewell@googlemail.com
cc9398cd42 ARM: Make double registers low/high safe 
This patch prevents taking the low/high part of a double-precision VFP register that has no corresponding single-precision VFP registers.

BUG=none
TEST=Added to test-disasm-arm.cc, test-assembler-arm.cc

Review URL: https://codereview.chromium.org/19560003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15885 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-07-25 15:04:38 +00:00
rodolph.perfetta@gmail.com
762157d697 ARM: Implement memcpy using NEON. 
Add support for a few NEON and ARM SIMD instructions and use them for various
memcpy operations.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/17858002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-07-10 15:32:39 +00:00
yangguo@chromium.org
02674ee414 Keep two empty lines between declarations for cpp files 
R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/18509003

Patch from Haitao Feng <haitao.feng@intel.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15510 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-07-05 09:52:11 +00:00
mstarzinger@chromium.org
f8db2414f2 Deprecate FACTORY helper macro. 
This removes the FACTORY helper macro to avoid accidental TLS access
when using the factory. Most internal code has access to the Isolate by
now whereas tests which are not performance critical still heavily use
TLS access through explicit Isolate::Current() calls.

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/16337005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14931 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-06-04 10:30:05 +00:00
dcarney@chromium.org
ff2a76b5d5 remove most V8_ALLOW_ACCESS_TO_* defines from test classes 
R=svenpanne@chromium.org
BUG=

Review URL: https://codereview.chromium.org/15964004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14849 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-05-28 11:54:52 +00:00
rodolph.perfetta@gmail.com
45ec481659 ARM: Smi refactoring and improvements. 
Refactoring:
 * consistent use of SmiTag/Untag
 * added a few Smi macros and helpers
Improvements
 * small optimisations (e.g. merging untag and cmp #0)
 * added fixed point to double conversion instructions for simpler conversions

More on the last point: a Smi can be seen as a fixed point number with the
a one bit fractional part. Fixed to double instructions allow us to convert
a Smi to a double without untagging.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/15085026

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14724 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-05-17 15:38:14 +00:00
dcarney@chromium.org
cf5ff5a14c first step to remove unsafe handles 
R=svenpanne@chromium.org
BUG=

Review URL: https://codereview.chromium.org/12729023

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14530 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-05-02 20:18:42 +00:00
m.m.capewell@googlemail.com
5c6b09e6c6 ARM: Enable VFP default NaN mode 
BUG=none
TEST=Default NaN tests added to test-assembler-arm.

Review URL: https://codereview.chromium.org/14109010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-04-15 15:55:47 +00:00
mstarzinger@chromium.org
dd70ce29d1 Unify the way cctest initalizes the VM for each test case. 
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/13483017

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14199 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-04-10 08:29:39 +00:00
danno@chromium.org
ffe7f6a1ba Remove ARM support for VFP2 
R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/13560007

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14159 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-04-07 04:34:20 +00:00
svenpanne@chromium.org
53310ac152 Added a version of the v8::HandleScope constructor with an Isolate and use that consistently. 
I tried to limit the use of v8::Isolate::GetCurrent() and v8::internal::Isolate::Current() as much as possible, but sometimes this would have involved restructuring tests quite a bit, which is better left for a separate CL.

BUG=v8:2487

Review URL: https://codereview.chromium.org/12716010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13953 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-03-15 12:06:53 +00:00
svenpanne@chromium.org
e4edbb0535 Cleaned up CpuFeature scope handling. 
First of all, it has nothing to do with Isolates, it is related to the assembler
at hand. Furthermore, the saving/restoring is platform-independent. Cleaned up
some platform-specific stuff on the way.

Note that there are some things which still need some cleanup, like e.g. using
EnumSet instead of uint64_t, making Probe() more uniform across platforms etc.,
but the CL is already big enough.

BUG=v8:2487

Review URL: https://codereview.chromium.org/12391055

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13823 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-03-05 10:48:16 +00:00
ulan@chromium.org
87265114c4 Emit VMLS for multiply-subtract on ARM. 
BUG=none

Review URL: https://chromiumcodereview.appspot.com/12319113
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13748 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-02-27 10:24:40 +00:00
svenpanne@chromium.org
fb6776e84a Made Isolate a mandatory parameter for everything Handle-related. 
Unified parameter order of CreateHandle with the rest of v8 on the way. A few
Isolate::Current()s had to be introduced, which is not nice, and not every place
will win a beauty contest, but we can clean this up later easily in smaller steps.

Review URL: https://codereview.chromium.org/12300018

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13717 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-02-25 14:46:09 +00:00
ulan@chromium.org
250ebdc2be ARM: Change signature for vmov.32 function in the assembler 
The assembler has 8 different vmov variants. The one for vmov.32 and for moving
an immediate into a double reg only differs in the type of the second
paremeter: vmov.32 takes an int, the other takes a double.

The situation is dangerous because C++ will happily implicitly convert between
int and double.

This patch changes the signature of the vmov.32 assembler function so that it
cannot be confused with the other vmovs.

BUG=none

Review URL: https://chromiumcodereview.appspot.com/12255031
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13668 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-02-14 12:28:02 +00:00
ulan@chromium.org
bed569b548 ARM: Make use of d16-d31 when available. 
Review URL: https://chromiumcodereview.appspot.com/11428137
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-01-23 16:29:48 +00:00
ulan@chromium.org
4403daca1a ARM: generate integer zero in a uniform manner. 
ARM generated integer zero as either Operand(0, RelocInfo::NONE32), or
Operand(0), or Operand::Zero(). My change makes it use only
Operand::Zero().

This has no functional impact, it's pure cleanup.

R= ulan@chromium.org

Review URL: https://chromiumcodereview.appspot.com/11745030
Patch from JF Bastien <jfb@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13318 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-01-07 09:43:12 +00:00
ulan@chromium.org
0606abbaab Rename RelocInfo::NONE to RelocInfo::NONE32. 
This CL only does renaming, nothing else.

Followup to:
https://chromiumcodereview.appspot.com/11695006/

There are now NONE and NONE64 RelocInfo types, but only ARM uses them
both at the same time. They were added in:
https://chromiumcodereview.appspot.com/11191029/

R= ulan@chromium.org

Review URL: https://chromiumcodereview.appspot.com/11744020
Patch from JF Bastien <jfb@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13311 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-01-04 10:56:24 +00:00
ulan@chromium.org
74492ab2d4 Emit VMLA for multiply-add on ARM 
Review URL: https://chromiumcodereview.appspot.com/11293061
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12958 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-11-14 11:01:18 +00:00
yangguo@chromium.org
59f212e7eb Relax requirement from VFP3 to VFP2 where possible. 
BUG=
TEST=

Review URL: https://chromiumcodereview.appspot.com/10818026

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12194 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-07-25 15:26:16 +00:00
svenpanne@chromium.org
4084e698c3 Fixed a bug in the chaining of fixup position 
The ARM and MIPS assemblers had a bug where they did not handle the last element
in the list of code positions correctly during the fixup of offsets for forward
jumps. This happened when the first instruction contained a forward jump to a
label, and that label was used in a forward jump later, too.

Unified the code for Assembler::next on ARM and MIPS while we were there.

Added test cases, even for ia32/x64, which seem to be correct, even I don't
fully understand why... %-}

BUG=v8:1644
Review URL: http://codereview.chromium.org/7786001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@9063 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-08-30 07:36:31 +00:00
karlklose@chromium.org
26fda9bf32 ARM: Optimisations for call, jump and untag. 
Improves some V8 benchmarks by a few % on A9.

Patch by ARM Ltd.

BUG=none
TEST=Added to test-assembler-arm.cc.

Review URL: http://codereview.chromium.org/6874010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7647 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-18 13:53:11 +00:00
sgjesse@chromium.org
6255476028 ARM: Add support load/store multiple VFP registers 
Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions.

R=karlklose@chromium.org, rodolph.perfetta@gmail.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//6691057

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-06 09:06:23 +00:00
vitalyr@chromium.org
179aef2b8f VM initialization refactoring. 
This patch introduces global once per-process initialization and moves
the OS and CPU setup there. This makes CPU features isolate-independent.

Review URL: http://codereview.chromium.org/6670119

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7462 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-31 16:17:37 +00:00
vitalyr@chromium.org
7976ca2cbc Merge isolates to bleeding_edge. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7271 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 20:35:07 +00:00
vitalyr@chromium.org
76e226f832 Revert r7268: it borked the history. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7269 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 19:41:05 +00:00
vitalyr@chromium.org
6ff7fdebd3 Merge isolates to bleeding_edge. 
Review URL: http://codereview.chromium.org/6685088

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 18:49:56 +00:00
karlklose@chromium.org
984135cb32 ARM: Improved double to integer truncation. 
Patch from ARM Ltd.

BUG=none
TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc

Review URL: http://codereview.chromium.org/6625084

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-15 11:19:13 +00:00
sgjesse@chromium.org
84de496896 Implements DoubleToI on ARM. Refactor some VFP code at the same time and 
fix the simulator behaviour.

BUG=none
TEST=added to cctest/test-assembler-arm.cc

Patch by Rodolph Perfetta from ARM Ltd.

Review URL: http://codereview.chromium.org/6368053


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6629 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-04 07:08:50 +00:00
ager@chromium.org
8198db7934 ARM: Add support for DoMathAbs with double inputs. 
Adds vabs instruction to simulator, assembler, disassembler and tests.

BUG=none
TEST=Added to cctest.

Review URL: http://codereview.chromium.org/6366016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-31 10:16:28 +00:00
sgjesse@chromium.org
26a8dc3818 ARM: Make the ARM hardware builder green 
Fix a bug in the --debug-code alignment check in the C entry stub.

Don't force the --debug-code flag in the ARM disassembler tests. The framework does support passing flags and the test runner will when running tests in debug mode.

Skip some deserialization tests which crashes from time to time.
Review URL: http://codereview.chromium.org/6393007

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-26 09:52:25 +00:00
erik.corry@gmail.com
8ebe8e4756 ARM: The Simulator will now handle different VFP rounding modes. RZ and RM are implemented. This is a commit of 
http://codereview.chromium.org/4295003/show for Alexander Rames of ARM.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5790 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-09 08:26:02 +00:00
erik.corry@gmail.com
0dcaac1939 Make Failure inherit from MaybeObject instead of Object. 
Review URL: http://codereview.chromium.org/3970005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5698 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-10-25 15:22:03 +00:00
whesse@chromium.org
7368ce808e Fix the ambigous Operand(0) for newer C++ compilers. 
Review URL: http://codereview.chromium.org/3351010/show
Committed for Thiago Farina <tfarina@chromium.org>


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5419 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-09-07 11:09:45 +00:00
erik.corry@gmail.com
66d13be5f9 Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-08-26 08:53:00 +00:00
erik.corry@gmail.com
6b20299bef Add support for vstr for single precision VFP register. This is a commit of http://codereview.chromium.org/3064045 for Rodolph Perfetta 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5281 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-08-17 08:43:45 +00:00
ager@chromium.org
74f9789f61 Landing for Rodolph Perfetta. 
Add support for saturation instruction (ARMv6 or above).
The byte array clamping code has been updated accordingly.

Review URL: http://codereview.chromium.org/3036008/show

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5106 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-21 07:42:51 +00:00
kaznacheev@chromium.org
0243bc875c Move serialized scope info from Code object to SharedFunctionInfo. 
The scope info is now stored in a FixedArray referenced from SharedFunctionInfo.


Review URL: http://codereview.chromium.org/2918001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5056 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-13 13:06:33 +00:00
erik.corry@gmail.com
67c0ec6f17 Update and improve support for ARMv7 bitfield instructions. 
This is a commit of http://codereview.chromium.org/2124022
for Rodolph Perfetta.  I changed the test in
test-assembler-arm.cc so it only runs if ARMv7 is supported.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-05-27 13:46:18 +00:00
kasperl@chromium.org
7d6a3b433f Merge the partial_snapshots branch back into bleeding_edge. For 
now, the custom call generator stuff is disabled.
Review URL: http://codereview.chromium.org/1094014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4217 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-03-23 11:40:38 +00:00
whesse@chromium.org
5428e036d1 Make ARM assembler VFP3 test pass on machines without VFP3 floating point hardware. 
Review URL: http://codereview.chromium.org/543187

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3691 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-01-25 15:17:58 +00:00
whesse@chromium.org
f88e7e82b7 Add vstr and vldr floating point load and store to ARM assembler, disassembler, and simulator. 
Review URL: http://codereview.chromium.org/545155

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3687 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-01-25 11:54:10 +00:00