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101 Commits

Author SHA1 Message Date
sgjesse@chromium.org
42a87564c3 ARM: Fix context save/restore for VFP registers. 
BUG=none
TEST=none

Review URL: http://codereview.chromium.org//7217011
Patch from Martyn Capewell <m.m.capewell@googlemail.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8357 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-06-22 06:24:34 +00:00
sgjesse@chromium.org
5efb84623b ARM: Clean up literal pool generation. 
Remove dead code, and generate pools less frequently.

BUG=none
TEST=none

Review URL: http://codereview.chromium.org//7108061
Patch from Martyn Capewell <m.m.capewell@googlemail.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8309 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-06-16 07:00:46 +00:00
mikhail.naganov@gmail.com
3b2470d296 Fix presubmit errors catched by a more recent version of cpplint.py. 
Mainly, there were errors concerning blank lines before and after class access
control sections [whitespace/blank_line].

BEFORE an access control section (e.g. public:, private:) there should be a
blank line (except for the section right after the class declaration).

AFTER an access control section there should be no blank line.

TBR=ager@chromium.org

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8193 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-06-07 07:17:46 +00:00
sgjesse@chromium.org
0e0b1b2da9 Optimise the deoptimisation check to improve performance on modern ARM cores. 
BUG=none
TEST=none

Committed: http://code.google.com/p/v8/source/detail?r=7909

Reverted in r7916.

Review URL: http://codereview.chromium.org//7021007

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7991 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-05-23 12:48:17 +00:00
fschneider@chromium.org
6db15ae34b Remove peephole optimiziations from IA32 and ARM assembler. 
They are not used with Crankshaft anymore.
Review URL: http://codereview.chromium.org/7003025

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7854 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-05-11 11:29:53 +00:00
whesse@chromium.org
d96dc0755b Add AST ID to RelocInfo for type-recording ICs. Changes 7644 and 7632, combined. 
BUG=
TEST=

Review URL: http://codereview.chromium.org/6902066

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7694 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-27 15:02:59 +00:00
jkummerow@chromium.org
bc8f6943bb Support Float64Arrays 
BUG=None
TEST=mjsunit/external-arrays.js; updated cctest; existing unit tests

Review URL: http://codereview.chromium.org/6879009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7675 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-21 07:15:43 +00:00
ricow@chromium.org
69a4c52bbf Revert revisions 7644 and 7632, they are causing assertion failures in interactive_ui_tests debug mode. 
Review URL: http://codereview.chromium.org/6873076

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7664 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-19 16:04:49 +00:00
whesse@chromium.org
46164ee24e Record AST ids in relocation info at spots where we collect dynamic type feedback. 
Review URL: http://codereview.chromium.org/6793016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7632 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-15 13:18:53 +00:00
sgjesse@chromium.org
75759805a9 ARM: Remove support for ABI prior to EABI 
The support for the old ABI is known to be broken and has been deprecated for some time now. Removed the instructions for loading and storing co-processor registers as they where only used to support the old ABI.

R=karlklose@chromium.org

BUG=v8:1316
TEST=

Review URL: http://codereview.chromium.org//6822025

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7565 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-11 09:04:30 +00:00
sgjesse@chromium.org
6255476028 ARM: Add support load/store multiple VFP registers 
Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions.

R=karlklose@chromium.org, rodolph.perfetta@gmail.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//6691057

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-06 09:06:23 +00:00
vitalyr@chromium.org
179aef2b8f VM initialization refactoring. 
This patch introduces global once per-process initialization and moves
the OS and CPU setup there. This makes CPU features isolate-independent.

Review URL: http://codereview.chromium.org/6670119

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7462 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-31 16:17:37 +00:00
ager@chromium.org
b69591bc0f Require an isolate parameter for most external reference creation to 
avoid TLS access in connection with external references.

Make the isolate accessible via the assembler.

Only for ia32 at this point. If this looks OK to you I will port it.

R=vitalyr@chromium.org

Review URL: http://codereview.chromium.org/6713074

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7305 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-22 13:20:04 +00:00
vitalyr@chromium.org
7976ca2cbc Merge isolates to bleeding_edge. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7271 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 20:35:07 +00:00
vitalyr@chromium.org
76e226f832 Revert r7268: it borked the history. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7269 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 19:41:05 +00:00
vitalyr@chromium.org
6ff7fdebd3 Merge isolates to bleeding_edge. 
Review URL: http://codereview.chromium.org/6685088

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 18:49:56 +00:00
vitalyr@chromium.org
2852c55356 Use a class field instead of global FLAG_debug_code in assember and 
macro assembler.

This way we can avoid changing the global flag value.

Review URL: http://codereview.chromium.org/6677044

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7178 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-15 14:49:10 +00:00
karlklose@chromium.org
984135cb32 ARM: Improved double to integer truncation. 
Patch from ARM Ltd.

BUG=none
TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc

Review URL: http://codereview.chromium.org/6625084

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-15 11:19:13 +00:00
sgjesse@chromium.org
bc9ddf20bb ARM: Port r7089 to ARM 
Ensure that there is always enough bytes between consequtive calls in optimized code to write a call instruction at the return points without overlapping.

Add a call to deoptimize all functions after running tests with --stress-opt. This will catch some issues with functions which cannot be forcefully deoptimized. Some of the tests failed on ARM with that change without the rest of the changes in this change.
Review URL: http://codereview.chromium.org/6661022

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7132 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-10 13:58:20 +00:00
sgjesse@chromium.org
1703b8a35c Implement int32 TypeRecordingBinaryOp on ARM. 
TEST=none
BUG=none

Patch by Rodolph Perfetta from ARM Ltd.

Review URL: http://codereview.chromium.org/6594009


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7014 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-02 09:31:42 +00:00
whesse@chromium.org
2642168331 ARM: Enable loads and stores of VFP registers with offsets >= 1024 bytes. 
Review URL: http://codereview.chromium.org/6530002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6830 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-17 10:07:13 +00:00
sgjesse@chromium.org
dabc590527 ARM: Add type-feedback recording for compare 
Change the comparison in the full code generator to use CompareIC instead of the CompareStub to record the types. This also implements the patching in the full code generator where the inlined smi code is de-activated by default to call the CompareIC once and then activating the inlined smi code by patching the code.

Fixed the smi comparison in the ICCompareStub.

Fixed ToBooleanStub to ensure that the scratch register used is not the input. Use r9 as default as that will never be input with Crankshaft.

Implemented lithium instruction CmpTAndBranch.

Make sure that the lithium instruction CmpID have operands in registrers as the current optimized code expects that.
Review URL: http://codereview.chromium.org/6461017

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6704 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-09 14:57:24 +00:00
sgjesse@chromium.org
84de496896 Implements DoubleToI on ARM. Refactor some VFP code at the same time and 
fix the simulator behaviour.

BUG=none
TEST=added to cctest/test-assembler-arm.cc

Patch by Rodolph Perfetta from ARM Ltd.

Review URL: http://codereview.chromium.org/6368053


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6629 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-04 07:08:50 +00:00
ager@chromium.org
8198db7934 ARM: Add support for DoMathAbs with double inputs. 
Adds vabs instruction to simulator, assembler, disassembler and tests.

BUG=none
TEST=Added to cctest.

Review URL: http://codereview.chromium.org/6366016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-31 10:16:28 +00:00
ager@chromium.org
0e183035a2 ARM: Merging constants in simulator and assembler header files and other cleanup. 
First stab at a general ARM cleanup patch. It merges ARM constants so that they can be used across simulator, assembler and disassembler, and tidies up some syntax and ambiguities.

BUG=none
TEST=none

Review URL: http://codereview.chromium.org/6274009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6483 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-26 08:32:54 +00:00
ager@chromium.org
ac320205b9 ARM: Fix ARM safepoint tables by ensuring that constant pools are not 
emitted as part of the safepoint tables.

Always emit the constant pool as part of generating deferred code
(whether or not there actually is any deferred code) and ASSERT that
there is no pending relocation info while using db and dd to write
tables.

Review URL: http://codereview.chromium.org/6360003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6347 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-17 12:45:39 +00:00
ager@chromium.org
0819ac76f6 Landing for Martyn Capewell. 
ARM: Implement DoInteger32ToDouble in lithium codegen. Clean up
temporary register use.

Code review URL: http://codereview.chromium.org/6257003/

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6339 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-17 07:26:36 +00:00
ager@chromium.org
0ec74d5829 Landing for Rodolph Perfetta. 
Implementing Math.floor and Math.sqrt for crankshaft.

BUG=none
TEST=none

Code review URL: http://codereview.chromium.org/6250002/

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6298 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-13 12:21:47 +00:00
sgjesse@chromium.org
8f54606109 ARM: Always use the overflow flag to check for NaNs participating in a floating point compare. 
Looks as if we don't need to use the vcmpe instruction instead of the vcmp, as the overflow FPSCR bit suits our purpose. If we at some point need vcmpe lte's implement it as a separate instruction.
Review URL: http://codereview.chromium.org/6197003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6277 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-12 07:47:13 +00:00
sgjesse@chromium.org
c4550bc6d5 ARM: Add instructions VFPCompareAndSetFlags and VFPCompareAndLoadFlags to macro assembler 
Also removed the SBit from the vcmp instruction as it is not part of the instruction.
Review URL: http://codereview.chromium.org/6117003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-11 12:45:25 +00:00
ager@chromium.org
5e3381c9c7 Landing for Martyn Capewell. 
ARM: Fix comparison of NaN values.

Enables the cumulative exception flag when comparing values, and uses it to
detect NaN results.

BUG=1023
TEST=none

Code review URL: http://codereview.chromium.org/6142004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6236 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-10 08:04:30 +00:00
sgjesse@chromium.org
71d863e5de Set a fixed scratch register for ARM code generation 
r9 is now set as a fixed scratch register for ARM code generation. removed some unneeded allocation of temporary registers and use the scratch register instead.
Review URL: http://codereview.chromium.org/5976014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6162 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-04 14:32:54 +00:00
kasperl@chromium.org
90b3370374 Update V8 to version 3.0 (re-land r5920). 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5922 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-12-07 11:31:57 +00:00
kasperl@chromium.org
51b494d096 Revert r5920. Will re-land shortly. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5921 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-12-07 11:01:02 +00:00
kasperl@chromium.org
e5860bd6a8 Update V8 to version 3.0. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5920 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-12-07 09:11:56 +00:00
sgjesse@chromium.org
0c064efdb0 Make randomized allocations along 64k granularity boundaries to avoid comitting unused memory. 
BUG=56036
TEST=None.

Patch by Justin Schuh <jschuh@chromium.org>

Review URL: http://codereview.chromium.org/3849004



git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5883 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-24 09:40:58 +00:00
erik.corry@gmail.com
f42de7dcae Implement Math.floor stub on ARM. Uses VFP when available. This is a commit of http://codereview.chromium.org/5075002/ for Martyn Capewell 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5835 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-17 09:24:44 +00:00
erik.corry@gmail.com
8ebe8e4756 ARM: The Simulator will now handle different VFP rounding modes. RZ and RM are implemented. This is a commit of 
http://codereview.chromium.org/4295003/show for Alexander Rames of ARM.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5790 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-09 08:26:02 +00:00
vegorov@chromium.org
9b96a9d592 Fix presubmit errors introduced by r5768. 
Review URL: http://codereview.chromium.org/4409003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5770 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-04 15:39:06 +00:00
whesse@chromium.org
861a66fb67 Fix a potential error in Add() macro-instruction on ARM. 
Review URL: http://codereview.chromium.org/4247004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5769 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-04 15:30:04 +00:00
vegorov@chromium.org
746d72420c Improve positions recording for calls. 
Review URL: http://codereview.chromium.org/4469002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5768 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-04 15:12:03 +00:00
ager@chromium.org
2122827893 Landing for Rodolph Perfetta. 
Fix the ARM simulator, the ARM disassembler and extend the stop feature. 
The stop feature in the simulator now support enabling, disabling and 
counting. 

BUG=None 
TEST=None 

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5723 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-10-28 07:35:07 +00:00
kmillikin@chromium.org
9c503a8330 Fix some inconsistent formatting. 
I noticed we sometimes had extra spaces before and after the "const"
keyword.  Probably the result of a search and replace gone wrong.

This is a whitespace only change.

Review URL: http://codereview.chromium.org/3427021

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5519 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-09-24 08:25:31 +00:00
erik.corry@gmail.com
66d13be5f9 Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-08-26 08:53:00 +00:00
erik.corry@gmail.com
6b20299bef Add support for vstr for single precision VFP register. This is a commit of http://codereview.chromium.org/3064045 for Rodolph Perfetta 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5281 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-08-17 08:43:45 +00:00
sgjesse@chromium.org
e61bd7bd26 ARM: backend opt for ToBoolean: JIT code generation for ToBool 
Upgraded the CodeGenerator::ToBoolean() function in the ARM backend to use complete JIT code generation and not make runtime calls to ToBool (when VFP is enabled). 

This change also includes the vcmp VFP instruction that supports a constant 0.0 as the second operand. 

Patch by Subrato K De <subratokde@codeaurora.org>



git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5267 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-08-16 07:52:49 +00:00
ager@chromium.org
a36bf8f017 Port inlined in-object property stores to ARM. 
Review URL: http://codereview.chromium.org/2878043

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5116 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-22 08:17:40 +00:00
ager@chromium.org
74f9789f61 Landing for Rodolph Perfetta. 
Add support for saturation instruction (ARMv6 or above).
The byte array clamping code has been updated accordingly.

Review URL: http://codereview.chromium.org/3036008/show

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5106 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-21 07:42:51 +00:00
erik.corry@gmail.com
8c767e02f9 ARM: Add support for the VFP mov literal instruction and mov 
between single VFP registers.  Math.pow implementation has
been updated with the new instructions.  This is a commit
of http://codereview.chromium.org/2813046/show for Rodolph
Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-08 12:38:02 +00:00
sgjesse@chromium.org
ff6c4fe680 ARM: Special code for raising to the power of an integer 
When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result.

Added support for the vmov instruction moving from one doubleword extension register to another.

Added some Math.pow tests which partially covers what is in the Sputnik tests.
Review URL: http://codereview.chromium.org/2804033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-30 12:22:15 +00:00