AuroraMiddleware/v8
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174 Commits

Author SHA1 Message Date
svenpanne@chromium.org
1b833ff35e Additional minor cleanup regarding CallWrapper: Use the null object pattern. 
Review URL: http://codereview.chromium.org/6909026

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7767 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-05-03 15:12:40 +00:00
svenpanne@chromium.org
b60baa0b70 Removed InvokeJSFlags enum, we already have InvokeFlag for the same purpose. 
Review URL: http://codereview.chromium.org/6880321

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7732 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-29 20:07:41 +00:00
sgjesse@chromium.org
00bc2db28f ARM: Support hardfloat in SCons build and make it a build time setting 
Add option armeabi to the SCons build for selecting the floating point variant to use. Also add externally defined CCFLAGS environment for all targets. Run test.py with option -S armeabi=hardfloat to test with hardfloat enabled.

Make selecting hardfloat EABI variant a build-time option instead of a runtime option.

Add a simple check of the EABI variant during V8 initialization to exit if the compilation was not configured correctly. The reason for this is that GCC does not provide a compile time symbol defining the EABI variant. This check is not fool-proof as it cannot check the compilation configuration used for the snapshot if any.

R=karlklose@chromium.org, erik.corry@gmail.com

BUG=none
TEST=none

Review URL: http://codereview.chromium.org//6905098

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7715 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-29 08:50:38 +00:00
whesse@chromium.org
d96dc0755b Add AST ID to RelocInfo for type-recording ICs. Changes 7644 and 7632, combined. 
BUG=
TEST=

Review URL: http://codereview.chromium.org/6902066

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7694 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-27 15:02:59 +00:00
karlklose@chromium.org
7ba01a83e9 Implement hardfloat calling convention in macro assembler and simulator. 
Review URL: http://codereview.chromium.org/6874007

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7693 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-27 14:29:25 +00:00
ricow@chromium.org
69a4c52bbf Revert revisions 7644 and 7632, they are causing assertion failures in interactive_ui_tests debug mode. 
Review URL: http://codereview.chromium.org/6873076

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7664 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-19 16:04:49 +00:00
karlklose@chromium.org
26fda9bf32 ARM: Optimisations for call, jump and untag. 
Improves some V8 benchmarks by a few % on A9.

Patch by ARM Ltd.

BUG=none
TEST=Added to test-assembler-arm.cc.

Review URL: http://codereview.chromium.org/6874010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7647 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-18 13:53:11 +00:00
whesse@chromium.org
46164ee24e Record AST ids in relocation info at spots where we collect dynamic type feedback. 
Review URL: http://codereview.chromium.org/6793016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7632 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-15 13:18:53 +00:00
karlklose@chromium.org
bb1fe3ed9c Revert revision 7582. 
The changes caused mozilla date test failures on ARM.

TBR=ager
Review URL: http://codereview.chromium.org/6833020

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7594 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-13 08:00:59 +00:00
karlklose@chromium.org
72fff00e48 ARM: Add optimization for constant RHS in DoMulI. 
Patch by ARM Ltd.

Review URL: http://codereview.chromium.org/6756033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7582 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-12 06:44:15 +00:00
sgjesse@chromium.org
75759805a9 ARM: Remove support for ABI prior to EABI 
The support for the old ABI is known to be broken and has been deprecated for some time now. Removed the instructions for loading and storing co-processor registers as they where only used to support the old ABI.

R=karlklose@chromium.org

BUG=v8:1316
TEST=

Review URL: http://codereview.chromium.org//6822025

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7565 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-11 09:04:30 +00:00
ager@chromium.org
95c76ed464 Remove some dead code. 
- virtual-frame*
- register-allocator*
- jump-target*
- most of codegen*
- AstOptimizer and fields on AST

There is a lot of additional cleanup that we should do but this gets
rid of a lot.

R=kmillikin@chromium.org
BUG=
TEST=

Review URL: http://codereview.chromium.org/6811012

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7542 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-07 14:42:37 +00:00
sgjesse@chromium.org
6255476028 ARM: Add support load/store multiple VFP registers 
Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions.

R=karlklose@chromium.org, rodolph.perfetta@gmail.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//6691057

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-06 09:06:23 +00:00
vitalyr@chromium.org
6952f68ee3 Fix non-ia32 build. 
Review URL: http://codereview.chromium.org/6771052

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-01 15:37:59 +00:00
vitalyr@chromium.org
179aef2b8f VM initialization refactoring. 
This patch introduces global once per-process initialization and moves
the OS and CPU setup there. This makes CPU features isolate-independent.

Review URL: http://codereview.chromium.org/6670119

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7462 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-31 16:17:37 +00:00
vitalyr@chromium.org
d89c753152 Only pass isolate parameter to C helper functions that need it. 
Review URL: http://codereview.chromium.org/6778018

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7450 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-30 18:05:16 +00:00
ager@chromium.org
1bdc8031fa Introduce accessors on builtins instance and use them to avoid TLS access when getting builtins. 
R=vitalyr@chromium.org

Review URL: http://codereview.chromium.org/6717018

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7327 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-23 13:40:07 +00:00
ager@chromium.org
b69591bc0f Require an isolate parameter for most external reference creation to 
avoid TLS access in connection with external references.

Make the isolate accessible via the assembler.

Only for ia32 at this point. If this looks OK to you I will port it.

R=vitalyr@chromium.org

Review URL: http://codereview.chromium.org/6713074

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7305 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-22 13:20:04 +00:00
sgjesse@chromium.org
4a2639e7ef Improved modulo operation in lithium as well as bailout on -0. 
TEST=none
BUG=none

Patch by Rodolph Perfetta from ARM Ltd.

Review URL: http://codereview.chromium.org/6612017


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7300 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-22 10:00:43 +00:00
karlklose@chromium.org
12615106d7 Revert r7288. 
TBR=ager
Review URL: http://codereview.chromium.org/6709060

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7292 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-21 16:10:05 +00:00
karlklose@chromium.org
93d4776d46 ARM: Add optimization for constant RHS in DoMulI. 
Patch by ARM Ltd.

Review URL: http://codereview.chromium.org/6708025

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7288 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-21 14:31:15 +00:00
vitalyr@chromium.org
7976ca2cbc Merge isolates to bleeding_edge. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7271 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 20:35:07 +00:00
vitalyr@chromium.org
76e226f832 Revert r7268: it borked the history. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7269 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 19:41:05 +00:00
vitalyr@chromium.org
6ff7fdebd3 Merge isolates to bleeding_edge. 
Review URL: http://codereview.chromium.org/6685088

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 18:49:56 +00:00
vitalyr@chromium.org
2852c55356 Use a class field instead of global FLAG_debug_code in assember and 
macro assembler.

This way we can avoid changing the global flag value.

Review URL: http://codereview.chromium.org/6677044

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7178 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-15 14:49:10 +00:00
karlklose@chromium.org
984135cb32 ARM: Improved double to integer truncation. 
Patch from ARM Ltd.

BUG=none
TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc

Review URL: http://codereview.chromium.org/6625084

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-15 11:19:13 +00:00
sgjesse@chromium.org
4dc80f788a ARM: Move the constant pool blocking for call instruction sequences 
The constant pool blocking for call instruction sequences is hoisted to the begof the function generating the call sequence.
Review URL: http://codereview.chromium.org/6690009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7155 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-14 12:32:20 +00:00
sgjesse@chromium.org
bc9ddf20bb ARM: Port r7089 to ARM 
Ensure that there is always enough bytes between consequtive calls in optimized code to write a call instruction at the return points without overlapping.

Add a call to deoptimize all functions after running tests with --stress-opt. This will catch some issues with functions which cannot be forcefully deoptimized. Some of the tests failed on ARM with that change without the rest of the changes in this change.
Review URL: http://codereview.chromium.org/6661022

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7132 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-10 13:58:20 +00:00
whesse@chromium.org
5a40de9b21 Add new ARM macro assembler function CompareRoot left out of previous commit. 
Review URL: http://codereview.chromium.org/6614015

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7042 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-03 12:21:37 +00:00
karlklose@chromium.org
64191ccc8d ARM: Implement untagged input for TranscendentalCacheStub. 
Review URL: http://codereview.chromium.org/6591073

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7028 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-02 14:40:38 +00:00
sgjesse@chromium.org
1703b8a35c Implement int32 TypeRecordingBinaryOp on ARM. 
TEST=none
BUG=none

Patch by Rodolph Perfetta from ARM Ltd.

Review URL: http://codereview.chromium.org/6594009


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7014 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-02 09:31:42 +00:00
sgjesse@chromium.org
7b0f5d4110 ARM: Support inlined version of %_FastAsciiArrayJoin on ARM 
Review URL: http://codereview.chromium.org/6594071

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6994 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-01 14:09:23 +00:00
antonm@chromium.org
4718466e48 Landing for Zaheer. 
Direct call accessor getter callbacks (arm implementation).

Original review: http://codereview.chromium.org/6462029/

Review URL: http://codereview.chromium.org/6576035

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6938 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-24 15:39:09 +00:00
sgjesse@chromium.org
15c9091a85 Fix presubmit error. 
TBR=ricow@chromium.org
Review URL: http://codereview.chromium.org/6580026

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6921 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-24 08:23:08 +00:00
sgjesse@chromium.org
acd4f89999 ARM: Port r6635 and r6659 
r6635: Remove the redundant load on every context lookup.
r6659: Do not compile the unreachable body of functions with illegal redeclarations.
Review URL: http://codereview.chromium.org/6572003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6920 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-24 07:17:43 +00:00
karlklose@chromium.org
16cc528316 ARM: Implement DoPower in the lithium code generator. 
Review URL: http://codereview.chromium.org/6532020

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6909 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-23 10:41:13 +00:00
ager@chromium.org
ea0dda89bb Unifying the handling of storing and loading from safepoint stack 
slots across architectures.

Review URL: http://codereview.chromium.org/6541051

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6862 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-21 11:29:45 +00:00
lrn@chromium.org
b4fd72b335 Change native RegExp call code to properly set C++ structures and 
to handle exceptions on return from RegExp.

BUG=1108
TEST=

Review URL: http://codereview.chromium.org/6489001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6794 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-15 13:53:51 +00:00
fschneider@chromium.org
ad70b7de39 Fix a potential crash bug in keyed calls for non-string keys. 
BUG=v8:1146

Review URL: http://codereview.chromium.org/6517010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6773 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-14 13:13:41 +00:00
sgjesse@chromium.org
505b46753e ARM: Add shift operations to the type recording binary operation stub 
Review URL: http://codereview.chromium.org/6471023

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6737 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-10 20:04:54 +00:00
sgjesse@chromium.org
dabc590527 ARM: Add type-feedback recording for compare 
Change the comparison in the full code generator to use CompareIC instead of the CompareStub to record the types. This also implements the patching in the full code generator where the inlined smi code is de-activated by default to call the CompareIC once and then activating the inlined smi code by patching the code.

Fixed the smi comparison in the ICCompareStub.

Fixed ToBooleanStub to ensure that the scratch register used is not the input. Use r9 as default as that will never be input with Crankshaft.

Implemented lithium instruction CmpTAndBranch.

Make sure that the lithium instruction CmpID have operands in registrers as the current optimized code expects that.
Review URL: http://codereview.chromium.org/6461017

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6704 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-09 14:57:24 +00:00
vegorov@chromium.org
721b60d3f5 Check for overflow when bumping new space's top in inlined allocation. 
BUG=v8:1109
TEST=test/mjsunit/regress/regress-1109.js

Review URL: http://codereview.chromium.org/6453005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6684 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-08 17:25:40 +00:00
antonm@chromium.org
aecb05354b Landing for Zaheer Ahmad. 
Direct call api functions (arm implementation)

See: http://codereview.chromium.org/6170001/

Review URL: http://codereview.chromium.org/6286078

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6639 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-04 13:43:38 +00:00
sgjesse@chromium.org
8d4e0bb39c ARM: Add support for and, or and xor to the type recording binary op stub. 
Review URL: http://codereview.chromium.org/6250126

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6631 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-04 10:52:19 +00:00
sgjesse@chromium.org
a453a3ce65 ARM: Add multiplication and modulus to the type recording binary operation stub. 
For now the smi part only handles power of two right hand side operands.

Fixed a bug when loading floating point value into core registers with VFP supported.
Review URL: http://codereview.chromium.org/6312059

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6560 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-01 16:38:25 +00:00
ager@chromium.org
8198db7934 ARM: Add support for DoMathAbs with double inputs. 
Adds vabs instruction to simulator, assembler, disassembler and tests.

BUG=none
TEST=Added to cctest.

Review URL: http://codereview.chromium.org/6366016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-31 10:16:28 +00:00
ager@chromium.org
0e183035a2 ARM: Merging constants in simulator and assembler header files and other cleanup. 
First stab at a general ARM cleanup patch. It merges ARM constants so that they can be used across simulator, assembler and disassembler, and tidies up some syntax and ambiguities.

BUG=none
TEST=none

Review URL: http://codereview.chromium.org/6274009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6483 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-26 08:32:54 +00:00
sgjesse@chromium.org
06515b6f1b ARM: Change BranchOnSmi/BranchOnNotSmi to JumpIfSmi/JumpIfNotSmi 
Review URL: http://codereview.chromium.org/6272019

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6477 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-26 07:44:45 +00:00
sgjesse@chromium.org
99a5b9f713 ARM: Initial type recording binary operation stub 
This implements the type recording binary operation stub for ARM. This first iteration only supports ADD. Handling of 32-bit integers is currently not implemented but just transitions. The generic case for now delegates to the generic binary operation stub.
Review URL: http://codereview.chromium.org/6342019

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6471 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-25 14:52:35 +00:00
sgjesse@chromium.org
161d631b5e Change ARM exit frame layout and alingment handling 
Change the ARM exit frame to have the same layout as the IA32 exit frame. This basically re-arranges the order of fp and sp and changes the sp location of the entry frame to hold the sp used by the gc and not the sp for popping the arguments. This removes the option of tearing down the frame and returning using one ldm instruction.

The main motivation for this is to avoid pushing an alignment word before generating the entry frame. The GC handling of optimized frames process the registers pushed as part of a safepoint and asumes that these are at the top of the frame, so if an alignment word is pushed this processing will be one off.

The alignment handling in the C entry stub have also been simplified. Now the value of lr is stored to a stack slot already reserved avoiding pushing it and keeping track of "frame skew".

This does result in more instructions in the exit frame on ARM, but we can look into improving this later.
Review URL: http://codereview.chromium.org/6247019

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6448 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-25 07:49:39 +00:00