AuroraMiddleware/v8
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30 Commits

Author SHA1 Message Date
ulan@chromium.org
74492ab2d4 Emit VMLA for multiply-add on ARM 
Review URL: https://chromiumcodereview.appspot.com/11293061
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12958 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-11-14 11:01:18 +00:00
svenpanne@chromium.org
1ea5db0ed3 Martyn Capewell <m.m.capewell@googlemail.com> 
Review URL: https://chromiumcodereview.appspot.com/10451037

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@11784 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-06-12 17:26:28 +00:00
erik.corry@gmail.com
b3e0761e38 Cosmetic changes ("set up" is a verb, "setup" is a noun). 
Review URL: http://codereview.chromium.org/9139051

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10399 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-01-13 13:09:52 +00:00
karlklose@chromium.org
b606195012 ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. 
Patch from ARM Ltd.

BUG=none
TEST=added to test/cctest/test-disasm-arm.cc

Original review at http://codereview.chromium.org/7013024/.

Review URL: http://codereview.chromium.org/7013027

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-05-12 14:44:49 +00:00
sgjesse@chromium.org
6255476028 ARM: Add support load/store multiple VFP registers 
Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions.

R=karlklose@chromium.org, rodolph.perfetta@gmail.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//6691057

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-06 09:06:23 +00:00
vitalyr@chromium.org
179aef2b8f VM initialization refactoring. 
This patch introduces global once per-process initialization and moves
the OS and CPU setup there. This makes CPU features isolate-independent.

Review URL: http://codereview.chromium.org/6670119

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7462 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-31 16:17:37 +00:00
vitalyr@chromium.org
7976ca2cbc Merge isolates to bleeding_edge. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7271 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 20:35:07 +00:00
vitalyr@chromium.org
76e226f832 Revert r7268: it borked the history. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7269 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 19:41:05 +00:00
vitalyr@chromium.org
6ff7fdebd3 Merge isolates to bleeding_edge. 
Review URL: http://codereview.chromium.org/6685088

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 18:49:56 +00:00
karlklose@chromium.org
984135cb32 ARM: Improved double to integer truncation. 
Patch from ARM Ltd.

BUG=none
TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc

Review URL: http://codereview.chromium.org/6625084

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-15 11:19:13 +00:00
ager@chromium.org
8198db7934 ARM: Add support for DoMathAbs with double inputs. 
Adds vabs instruction to simulator, assembler, disassembler and tests.

BUG=none
TEST=Added to cctest.

Review URL: http://codereview.chromium.org/6366016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-31 10:16:28 +00:00
erik.corry@gmail.com
ca7a438713 Improve support for vmrs/vmsr in ARM disassembler. This is a commit of http://codereview.chromium.org/4904001 for Martyn Capewell. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5824 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-15 10:21:57 +00:00
erik.corry@gmail.com
66d13be5f9 Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-08-26 08:53:00 +00:00
ager@chromium.org
74f9789f61 Landing for Rodolph Perfetta. 
Add support for saturation instruction (ARMv6 or above).
The byte array clamping code has been updated accordingly.

Review URL: http://codereview.chromium.org/3036008/show

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5106 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-21 07:42:51 +00:00
erik.corry@gmail.com
8c767e02f9 ARM: Add support for the VFP mov literal instruction and mov 
between single VFP registers.  Math.pow implementation has
been updated with the new instructions.  This is a commit
of http://codereview.chromium.org/2813046/show for Rodolph
Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-08 12:38:02 +00:00
sgjesse@chromium.org
ff6c4fe680 ARM: Special code for raising to the power of an integer 
When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result.

Added support for the vmov instruction moving from one doubleword extension register to another.

Added some Math.pow tests which partially covers what is in the Sputnik tests.
Review URL: http://codereview.chromium.org/2804033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-30 12:22:15 +00:00
sgjesse@chromium.org
fd5a7b37a2 ARM: Fix disassembly of double registers 
Added a few disassembler tests for vadd, vsub, vmul and vdiv.
Review URL: http://codereview.chromium.org/2823036

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-30 08:46:19 +00:00
sgjesse@chromium.org
65018d9123 ARM: Use the vsqrt instruction when available 
vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each.
Review URL: http://codereview.chromium.org/2885002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-29 09:40:36 +00:00
erik.corry@gmail.com
53340b2624 Add movw and movt support for ARMv7. This includes some code from 
Zhang Kun.  For now we only emit movw and movt in places where no
relocation is needed.  Small performance boost (around 0.5%).
Also adds support for turning ALU operations (eor etc.) with
large immediates into mvn or movw followed by a register-based
ALU operation.
Review URL: http://codereview.chromium.org/2821014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-22 08:38:32 +00:00
erik.corry@gmail.com
142de62819 ARM: Be more smart about switching instructions when immediates 
don't fit in the instruction.  Use ubfx and sbfx more.
Review URL: http://codereview.chromium.org/2826001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4855 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-14 11:20:36 +00:00
erik.corry@gmail.com
67c0ec6f17 Update and improve support for ARMv7 bitfield instructions. 
This is a commit of http://codereview.chromium.org/2124022
for Rodolph Perfetta.  I changed the test in
test-assembler-arm.cc so it only runs if ARMv7 is supported.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-05-27 13:46:18 +00:00
sgjesse@chromium.org
de69f5beba Add support for bkpt instruction 
The bkpt instruction is now supported by both the disassembler and the simulator. In the simulator it breaks to the native debugger if any like int3 on Intel.

Moved the handling of the miscellaneous instructions to a separate part.

Review URL: http://codereview.chromium.org/1576026


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4360 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-04-08 13:30:48 +00:00
erik.corry@gmail.com
038f9074bc Reapply ARM root array change to reduce const pool size 
by using r10 to point to a list of common root objects.
This time we also disable a debugger test on ARM that
has never worked, but with this change sometimes
crashes.
Review URL: http://codereview.chromium.org/174317

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2009-08-24 11:57:57 +00:00
feng@chromium.org
33fb11c12f Revert commit 2701 per Erik Corry's request. 
Original CL:

http://codereview.chromium.org/171041
Review URL: http://codereview.chromium.org/171089

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2702 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2009-08-18 00:12:26 +00:00
whesse@chromium.org
349dc04a5d Use root array to load roots in generated ARM code. 
This cuts down on code size and reloc work.
Review URL: http://codereview.chromium.org/171041

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2701 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2009-08-17 14:31:49 +00:00
kasperl@chromium.org
d8c56a7fc4 Fix ARM build. 
TBR=olehougaard@chromium.org
Review URL: http://codereview.chromium.org/28115

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@1366 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2009-02-25 16:13:57 +00:00
iposva@chromium.org
779af439ec Backport the changes from the readability review. 
Review URL: http://codereview.chromium.org/8939

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@700 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2008-11-05 19:18:10 +00:00
christian.plesner.hansen@gmail.com
66b18b9975 Fixed arm disassembler build problems. 
Fixed lint issue in platform-macos.

Review URL: http://codereview.chromium.org/1941

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@287 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2008-09-11 16:41:19 +00:00
christian.plesner.hansen@gmail.com
9bed566bdb Changed copyright header from google inc. to v8 project authors. 
Added presubmit step to check copyright.



git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@242 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2008-09-09 20:08:45 +00:00
christian.plesner.hansen
c42f5829a1 Included mjsunit JavaScript test suite and C++ unit tests. 
In the shell sample don't print the result of executing a script, only
evaluating expressions.

Fixed issue when building samples on Windows using a shared V8
library.  Added visibility option on Linux build which makes the
generated library 18% smaller.

Changed build system to accept multiple build modes in one build and
generate seperate objects, libraries and executables for each mode.

Removed deferred negation optimization (a * -b => -(a * b)) since this
visibly changes operand conversion order.

Improved parsing performance by introducing stack guard in preparsing.
Without a stack guard preparsing always bails out with stack overflow.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2008-08-22 13:33:59 +00:00