Commit Graph

27 Commits

Author SHA1 Message Date
bbudge
8c8600db2e [turbofan] Rename floating point register / slot methods.
Renames IsDouble* predicates to IsFP*.
Adds specific IsFloat*, IsDouble*, and IsSimd128* predicates.
Adds specific GetFloatRegister, GetDoubleRegister, and
GetSimd128Register methods.

This is mostly a mechanical renaming of IsDouble* to IsFP* methods.

This shouldn't change code generation at all. All fp registers are still
treated as double registers.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/1959763002
Cr-Commit-Position: refs/heads/master@{#36146}
2016-05-10 15:20:28 +00:00
jarin
bb2a830deb [turbofan] Make MachineType a pair of enums.
MachineType is now a class with two enum fields:
- MachineRepresentation
- MachineSemantic

Both enums are usable on their own, and this change switches some places from using MachineType to use just MachineRepresentation. Most notably:
- register allocator now uses just the representation.
- Phi and Select nodes only refer to representations.

Review URL: https://codereview.chromium.org/1513543003

Cr-Commit-Position: refs/heads/master@{#32738}
2015-12-10 09:03:53 +00:00
jochen
6f472db65a Disable soon to be deprecated APIs per default for v8
Embedders still can use those APIs by default

test-api.cc still has an exception to use the old APIs...

BUG=v8:4143
R=vogelheim@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/1505803004

Cr-Commit-Position: refs/heads/master@{#32701}
2015-12-09 10:35:04 +00:00
ishell
7d7eee513a [presubmit] Enabling readability/inheritance linter checking.
Review URL: https://codereview.chromium.org/1412223018

Cr-Commit-Position: refs/heads/master@{#31785}
2015-11-04 13:08:42 +00:00
mstarzinger
16f133001f Move compiler cctests into v8::internal::compiler namespace.
This moves all cctest files for the compiler to live in the same
namespace as the components they are testing. Hence we can avoid the
forbidden using directives pulling in entire namespaces.

From the Google C++ style guide: "You may not use a using-directive to
make all names from a namespace available". This would be covered by
presubmit linter checks if build/namespaces were not blacklisted.

R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1424943004

Cr-Commit-Position: refs/heads/master@{#31671}
2015-10-30 09:16:39 +00:00
mstarzinger
4a2bb8903b Remove deprecated API usage from compiler cctests.
R=jochen@chromium.org

Review URL: https://codereview.chromium.org/1408283006

Cr-Commit-Position: refs/heads/master@{#31630}
2015-10-28 13:09:55 +00:00
akos.palfi
8eabcb3fb6 Fix debug mode test failures on MIPS and PPC after f1aa5562.
TEST=cctest/test-gap-resolver/FuzzResolver,unittests/MoveOptimizerTest.RemovesRedundantExplicit
BUG=

Review URL: https://codereview.chromium.org/1403373016

Cr-Commit-Position: refs/heads/master@{#31629}
2015-10-28 13:04:43 +00:00
danno
f1aa556278 [turbofan] Create ExplicitOperands to specify operands without virtual registers
Up until now, if one wanted to specify an explicit stack location                                                                                                                                                                                                or register as an operand for an instruction, it had to also be
explicitly associated with a virtual register as a so-called
FixedRegister or FixedStackSlot.

For the implementation of tail calls, the plan is to use the gap
resolver needs to shuffle stack locations from the caller to the
tail-called callee. In order to do this, it must be possible to
explicitly address operand locations on the stack that are not
associated with virtual registers.

This CL introduces ExplictOperands, which can specify a specific
register or stack location that is not associated with virtual
register. This will allow tail calls to specify the target
locations for the necessary stack moves in the gap for the tail
call without the core register allocation having to know about
the target of the stack moves at all.

In the process this CL:
* creates a new Operand kind, ExplicitOperand, with which
  instructions can specify register and stack slots without an
  associated virtual register.
* creates a LocationOperand class from which AllocatedOperand and
  ExplicitOperand are derived and provides a common interface to
  get Register, DoubleRegister and spill slot information.
* removes RegisterOperand, DoubleRegisterOperand,
  StackSlotOperand and DoubleStackSlotOperand, they are subsumed
  by LocationOperand.
* addresses a cleanup TODO in AllocatedOperand to reduce the
  redundancy of AllocatedOperand::Kind by using machine_type() to
  determine if an operand corresponds to a general purpose or
  double register.

BUG=v8:4076
LOG=n

Review URL: https://codereview.chromium.org/1389373002

Cr-Commit-Position: refs/heads/master@{#31603}
2015-10-27 13:27:00 +00:00
chunyang.dai
5978b926c6 For some platform such as X87, Crankshaft and Turbofan needs to use different
register configurations currently. This CL provides a mechanism so that
    optimizing compilers can select different Register Configuration.

BUG=

Review URL: https://codereview.chromium.org/1405673003

Cr-Commit-Position: refs/heads/master@{#31476}
2015-10-22 13:24:49 +00:00
danno
5cf1c0bcf6 Re-reland: Remove register index/code indirection
Previous to this patch, both the lithium and TurboFan register
allocators tracked allocated registers by "indices", rather than
the register codes used elsewhere in the runtime. This patch
ensures that codes are used everywhere, and in the process cleans
up a bunch of redundant code and adds more structure to how the
set of allocatable registers is defined.

Some highlights of changes:

* TurboFan's RegisterConfiguration class moved to V8's top level
  so that it can be shared with Crankshaft.
* Various "ToAllocationIndex" and related methods removed.
* Code that can be easily shared between Register classes on
  different platforms is now shared.
* The list of allocatable registers on each platform is declared
  as a list rather than implicitly via the register index <->
  code mapping.

Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2
Cr-Commit-Position: refs/heads/master@{#30913}

Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf
Cr-Commit-Position: refs/heads/master@{#31075}

Review URL: https://codereview.chromium.org/1287383003

Cr-Commit-Position: refs/heads/master@{#31087}
2015-10-02 16:55:22 +00:00
danno
00e07b0057 Revert of Reland: Remove register index/code indirection (patchset #20 id:380001 of https://codereview.chromium.org/1287383003/ )
Reason for revert:
Failures on MIPS

Original issue's description:
> Remove register index/code indirection
>
> Previous to this patch, both the lithium and TurboFan register
> allocators tracked allocated registers by "indices", rather than
> the register codes used elsewhere in the runtime. This patch
> ensures that codes are used everywhere, and in the process cleans
> up a bunch of redundant code and adds more structure to how the
> set of allocatable registers is defined.
>
> Some highlights of changes:
>
> * TurboFan's RegisterConfiguration class moved to V8's top level
>   so that it can be shared with Crankshaft.
> * Various "ToAllocationIndex" and related methods removed.
> * Code that can be easily shared between Register classes on
>   different platforms is now shared.
> * The list of allocatable registers on each platform is declared
>   as a list rather than implicitly via the register index <->
>   code mapping.
>
> Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2
> Cr-Commit-Position: refs/heads/master@{#30913}
>
> Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf
> Cr-Commit-Position: refs/heads/master@{#31075}

TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true

Review URL: https://codereview.chromium.org/1380863004

Cr-Commit-Position: refs/heads/master@{#31083}
2015-10-02 15:37:06 +00:00
danno
7b7a8205d9 Remove register index/code indirection
Previous to this patch, both the lithium and TurboFan register
allocators tracked allocated registers by "indices", rather than
the register codes used elsewhere in the runtime. This patch
ensures that codes are used everywhere, and in the process cleans
up a bunch of redundant code and adds more structure to how the
set of allocatable registers is defined.

Some highlights of changes:

* TurboFan's RegisterConfiguration class moved to V8's top level
  so that it can be shared with Crankshaft.
* Various "ToAllocationIndex" and related methods removed.
* Code that can be easily shared between Register classes on
  different platforms is now shared.
* The list of allocatable registers on each platform is declared
  as a list rather than implicitly via the register index <->
  code mapping.

Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2
Cr-Commit-Position: refs/heads/master@{#30913}

Review URL: https://codereview.chromium.org/1287383003

Cr-Commit-Position: refs/heads/master@{#31075}
2015-10-02 13:59:06 +00:00
danno
3ac27431a9 Revert of Remove register index/code indirection (patchset #17 id:320001 of https://codereview.chromium.org/1287383003/ )
Reason for revert:
Failures on greedy RegAlloc, Fuzzer

Original issue's description:
> Remove register index/code indirection
>
> Previous to this patch, both the lithium and TurboFan register
> allocators tracked allocated registers by "indices", rather than
> the register codes used elsewhere in the runtime. This patch
> ensures that codes are used everywhere, and in the process cleans
> up a bunch of redundant code and adds more structure to how the
> set of allocatable registers is defined.
>
> Some highlights of changes:
>
> * TurboFan's RegisterConfiguration class moved to V8's top level
>   so that it can be shared with Crankshaft.
> * Various "ToAllocationIndex" and related methods removed.
> * Code that can be easily shared between Register classes on
>   different platforms is now shared.
> * The list of allocatable registers on each platform is declared
>   as a list rather than implicitly via the register index <->
>   code mapping.
>
> Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2
> Cr-Commit-Position: refs/heads/master@{#30913}

TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true

Review URL: https://codereview.chromium.org/1365073002

Cr-Commit-Position: refs/heads/master@{#30914}
2015-09-24 13:39:03 +00:00
danno
80bc6f6e11 Remove register index/code indirection
Previous to this patch, both the lithium and TurboFan register
allocators tracked allocated registers by "indices", rather than
the register codes used elsewhere in the runtime. This patch
ensures that codes are used everywhere, and in the process cleans
up a bunch of redundant code and adds more structure to how the
set of allocatable registers is defined.

Some highlights of changes:

* TurboFan's RegisterConfiguration class moved to V8's top level
  so that it can be shared with Crankshaft.
* Various "ToAllocationIndex" and related methods removed.
* Code that can be easily shared between Register classes on
  different platforms is now shared.
* The list of allocatable registers on each platform is declared
  as a list rather than implicitly via the register index <->
  code mapping.

Review URL: https://codereview.chromium.org/1287383003

Cr-Commit-Position: refs/heads/master@{#30913}
2015-09-24 12:53:13 +00:00
dcarney
81345f1a2c Reland: [turbofan] add MachineType to AllocatedOperand
- allows the optimization of emitted gap move code since the representation of the value in the register is known
- necessary preparation for vector register allocation
- prepare for slot sharing for any value of the same byte width

TBR=jarin@chromium.org
BUG=

Review URL: https://codereview.chromium.org/1111323003

Cr-Commit-Position: refs/heads/master@{#28140}
2015-04-29 19:36:25 +00:00
machenbach
7eccb18148 Revert of [turbofan] add MachineType to AllocatedOperand (patchset #17 id:310001 of https://codereview.chromium.org/1087793002/)
Reason for revert:
[Sheriff] Breaks compile on chromium asan and v8 msan:
http://build.chromium.org/p/client.v8/builders/Linux%20ASAN%20Builder/builds/3446
http://build.chromium.org/p/client.v8/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20MSAN/builds/2085

Original issue's description:
> [turbofan] add MachineType to AllocatedOperand
>
> - allows the optimization of emitted gap move code since the representation of the value in the register is known
> - necessary preparation for vector register allocation
> - prepare for slot sharing for any value of the same byte width
>
> BUG=
>
> Committed: https://crrev.com/3a025d1ab6437559f86a464767aa03d2d9789f6f
> Cr-Commit-Position: refs/heads/master@{#28137}

TBR=jarin@chromium.org,dcarney@chromium.org
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=

Review URL: https://codereview.chromium.org/1119483003

Cr-Commit-Position: refs/heads/master@{#28139}
2015-04-29 18:28:47 +00:00
dcarney
3a025d1ab6 [turbofan] add MachineType to AllocatedOperand
- allows the optimization of emitted gap move code since the representation of the value in the register is known
- necessary preparation for vector register allocation
- prepare for slot sharing for any value of the same byte width

BUG=

Review URL: https://codereview.chromium.org/1087793002

Cr-Commit-Position: refs/heads/master@{#28137}
2015-04-29 14:46:19 +00:00
Ross McIlroy
063fc25122 Replace OVERRIDE->override and FINAL->final since we now require C++11.
R=jochen@chromium.org

Review URL: https://codereview.chromium.org/1088993003

Cr-Commit-Position: refs/heads/master@{#27937}
2015-04-20 13:08:14 +00:00
dcarney
00aec79079 [turbofan] cleanup ParallelMove
- make ParallelMove into a ZoneVector, removing an annoying level of indirection
- make MoveOperands hold InstructionOperands instead of pointers, so there's no more operand aliasing for moves
- opens up possibility of storing MachineType in allocated operands

R=bmeurer@chromium.org
BUG=

Review URL: https://codereview.chromium.org/1081373002

Cr-Commit-Position: refs/heads/master@{#27842}
2015-04-15 12:36:27 +00:00
dcarney
8392d9c43b [turbofan] Make AllocatedOperand an InstructionOperand::Kind.
This is preparatory work to have MachineTypes encoded in AllocatedOperands.

Review URL: https://codereview.chromium.org/1075863002

Cr-Commit-Position: refs/heads/master@{#27698}
2015-04-09 10:40:43 +00:00
dcarney
07ff6d9f22 [turbofan] cleanup InstructionOperand a little
- ConstantOperand was using a too-small field too store its virtual register
- drop ConvertTo, replace it with simple copy
- split AllocatedOperand off from Immediate and Constant to make assignment clearer, also paving the way for small Immediates
- put zone first in *Operand::New
- driveby: drop delayed ssa deconstruction experiment

R=titzer@chromium.org
BUG=

Review URL: https://codereview.chromium.org/1050803002

Cr-Commit-Position: refs/heads/master@{#27692}
2015-04-09 09:15:32 +00:00
dcarney
996fa7d36e [turbofan] Remove global InstructionOperand caches.
Review URL: https://codereview.chromium.org/904693002

Cr-Commit-Position: refs/heads/master@{#26479}
2015-02-06 09:00:50 +00:00
dcarney@chromium.org
7cb25f5020 [turbofan] add RegisterConfiguration to decouple arch specific register layouts from compiler
R=bmeurer@chromium.org

BUG=

Review URL: https://codereview.chromium.org/694313002

Cr-Commit-Position: refs/heads/master@{#25097}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25097 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-04 09:22:32 +00:00
bmeurer@chromium.org
3eebdc3264 Replace OStream with std::ostream.
Review URL: https://codereview.chromium.org/618643002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24319 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-09-30 10:29:32 +00:00
bmeurer@chromium.org
30f18f0f7d Use Chrome compatible naming for compiler specifics.
Less useless creativity is best creativity!

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/526223002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23579 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-09-02 07:07:52 +00:00
bmeurer@chromium.org
bcbb39e0ef Fix android debug build.
TBR=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/430123002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22743 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-07-31 09:30:16 +00:00
danno@chromium.org
a1383e2250 Land the Fan (disabled)
R=mstarzinger@chromium.org

Review URL: https://codereview.chromium.org/426233002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22709 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-07-30 13:54:45 +00:00