AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity
16,403 Commits 1 Branch 0 Tags 839 MiB
fc437f4007
Commit Graph

23 Commits

Author SHA1 Message Date
Jacob.Bramley@arm.com
e876dab9ad ARM64: Fix and improve MacroAssembler::Printf. 
- W-sized values passed to Printf are now handled correctly by the
    simulator. In AAPCS64, int32_t and int64_t are passed in the same
    way, so this didn't affect non-simulator builds.
  - Since Printf now records the type and size of each argument, it is
    possible to mix argument types.
  - It is now possible to print the stack pointer. There is only one
    remaining restriction: The `csp` register cannot be printed unless
    it is the current stack pointer. This is because it is modified by
    BumpSystemStackPointer when the caller-saved registers are
    preserved.

BUG=
R=rmcilroy@chromium.org

Review URL: https://codereview.chromium.org/268353005

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21272 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-12 15:44:21 +00:00
yangguo@chromium.org
3ccedf8952 Clean up debugger flags. 
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/261253005

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21270 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-12 13:47:01 +00:00
verwaest@chromium.org
ed64101bc7 Reland and fix r21225 and r21226 
BUG=
R=ishell@chromium.org

Review URL: https://codereview.chromium.org/272203002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21232 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-09 16:18:58 +00:00
ishell@chromium.org
cb1a32885c [Sheriff] This reverts commits r21225 and r21226 for breaking Linux64 build. 
Revert "Make BitField3 a raw uint32 field, and move to the start of the map."
Revert "Make space available in bf3 by moving FunctionWithPrototype to bf1"

TBR=verwaest@chromium.org

Review URL: https://codereview.chromium.org/278883002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21227 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-09 14:28:59 +00:00
verwaest@chromium.org
ec195cd929 Make BitField3 a raw uint32 field, and move to the start of the map. 
BUG=
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/272163002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21225 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-09 13:18:25 +00:00
rmcilroy@chromium.org
2ba3716e4a Reland - Arm64: Ensure that csp is always aligned to 16 byte values even if jssp is not. 
Even although the Arm64 specification specifies that csp
only needs to be aligned to 16 bytes if it is dereferenced, some
implementations show poor performance.

Also makes the following change:
 - Enable CPU support for arm64 to enable probing of cpu implementer and cpu part.
 - Add ALWAYS_ALIGN_CSP CpuFeature for Arm64 and set it based on runtime probing of the cpu imp
 - Rename PrepareForPush and PrepareForPop to PushPreamble and PopPostamble and move PopPostabl

Original Review URL: https://codereview.chromium.org/264773004

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/271543004

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21221 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-09 12:51:52 +00:00
bmeurer@chromium.org
11f0e77562 Revert "Arm64: Ensure that csp is always aligned to 16 byte values even if jssp is not." and "Arm64: Fix check errors on Arm64 debug after r21177.". 
This reverts commit r21177 and r21179 for breaking the arm64 build.

TBR=rmcilroy@chromium.org

Review URL: https://codereview.chromium.org/271623002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21184 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-07 06:40:50 +00:00
rmcilroy@chromium.org
53bf126817 Arm64: Ensure that csp is always aligned to 16 byte values even if jssp is not. 
Even although the Arm64 specification specifies that csp
only needs to be aligned to 16 bytes if it is dereferenced, some implementations show poor performance if csp is every set to a non-aligned value.  This CL ensures that csp is always aligned to 16 byte values on these platforms and adds checks to ensure this in debug mode.

Also makes the following change:
 - Enable CPU support for arm64 to enable probing of cpu implementer and cpu part.
 - Add ALWAYS_ALIGN_CSP CpuFeature for Arm64 and set it based on runtime probing of the cpu implementer.
 - Rename PrepareForPush and PrepareForPop to PushPreamble and PopPostamble and move PopPostable after the pop.
 -

R=jacob.bramley@arm.com, ulan@chromium.org

Review URL: https://codereview.chromium.org/264773004

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21177 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-06 15:56:17 +00:00
mvstanton@chromium.org
f2903b6f6c Fix for 3303 MultithreadedParallelIsolates has a race condition. 
The fix is to make the code aging sequence hang off the isolate.

BUG=v8:3303
R=svenpanne@chromium.org
LOG=N

Review URL: https://codereview.chromium.org/261953002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21165 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-06 11:25:37 +00:00
Jacob.Bramley@arm.com
77d6bca46f ARM64: Use default-NaN mode to canonicalize NaNs. 
BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/255343004

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21156 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-06 08:05:27 +00:00
bmeurer@chromium.org
d4b533d41b Bulk update of Google copyright headers in source files. 
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/259183002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21035 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-29 06:42:26 +00:00
m.m.capewell@googlemail.com
dc438dceec ARM64: Rename TryConvertDoubleToInt64 function 
There are two TryConvertDoubleToInt64 functions: one rounds, the other checks
if a double can be exactly represented as an int. This patch renames the second
instance to reflect its purpose more clearly.

BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/258933008

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21020 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-28 13:33:14 +00:00
yangguo@chromium.org
cb2f43cb14 Always include debugger support. 
Motivation: we do not have test coverage for debuggersupport=off.

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/256653004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20969 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-25 11:00:37 +00:00
Jacob.Bramley@arm.com
1bdc421adf ARM64: Slightly improve MacroAssembler::Allocate. 
BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/247533005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20946 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-24 14:55:28 +00:00
Jacob.Bramley@arm.com
74d49a1e7e ARM64: Preserve x8 and x9 when necessary. 
Fix a couple of places were x8 and x9 are excluded from lists of saved
registers. These are caller-saved registers, so C code can corrupt them.

x8 and x9 were originally reserved for debug code in the ARM64 port, so
we didn't bother preserving them, but they are now normal allocatable
registers.

BUG=v8:3263
LOG=N
R=rmcilroy@chromium.org, ulan@chromium.org

Review URL: https://codereview.chromium.org/233373002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20658 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-10 15:47:45 +00:00
alexandre.rames@arm.com
622ddd3495 ARM64: Introduce a version of ADR handling distant targets. 
This fixes an out-of-range label error for an ADR instruction in the
mozilla/data/js1_5/Regress/regress-280769-2.js test.

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/222433002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20545 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-07 12:33:03 +00:00
alexandre.rames@arm.com
72288a68dd ARM64: Use direct deoptimization exits. 
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/225703002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20515 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-04 13:41:12 +00:00
alexandre.rames@arm.com
1f38f42ef1 ARM64: Fixes and more support for FRINT<X> instructions. 
Fix simulation and tests for the [-0.5, -0.0[ range for FRINTA and FRINTN, and
add support for FRINTM.

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/223843002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20487 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-03 14:30:44 +00:00
alexandre.rames@arm.com
989683d479 ARM64: Optimize AllocateHeapNumber to use STP. 
R=jochen@chromium.org

Review URL: https://codereview.chromium.org/216933003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20356 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-31 14:06:42 +00:00
ulan@chromium.org
d334c09bf4 ARM64: block veneer pool in InstructionAccurateScope. 
TEST=mozilla/ecma_3/RegExp/regress-169497
TBR=alexandre.rames@arm.com

Review URL: https://codereview.chromium.org/211323003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20255 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-25 16:14:46 +00:00
alexandre.rames@arm.com
e577a18bd8 ARM64: Fix Register and FPRegister copy constructors. 
This issue was introduced in r19156.

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/207743003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20212 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-24 17:41:37 +00:00
m.m.capewell@googlemail.com
86f5302002 ARM64: push/pop registers in stubs for safepoints 
BUG=

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/209933003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20210 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-24 16:41:37 +00:00
jochen@chromium.org
2ce0bebba1 Rename A64 port to ARM64 port 
BUG=354405
R=ulan@chromium.org, rodolph.perfetta@arm.com
LOG=y

Review URL: https://codereview.chromium.org/207823003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20148 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-21 09:28:26 +00:00