f4fb702569
Denver supports a coherent cache mechanism. There is no need to clean the D cache and invalidate I cache. MTS has to check the translation anytime there is an I cache invalidate and this time can be saved by making FlushICache a NOP. The patch improves Octane by roughly 3-4% on Denver. Review URL: https://codereview.chromium.org/797233002 Cr-Commit-Position: refs/heads/master@{#25898}
70 lines
2.0 KiB
C++
70 lines
2.0 KiB
C++
// Copyright 2006-2009 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// CPU specific code for arm independent of OS goes here.
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#ifdef __arm__
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#ifdef __QNXNTO__
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#include <sys/mman.h> // for cache flushing.
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#undef MAP_TYPE
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#else
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#include <sys/syscall.h> // for cache flushing.
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#endif
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#endif
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#include "src/v8.h"
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#if V8_TARGET_ARCH_ARM
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#include "src/assembler.h"
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#include "src/macro-assembler.h"
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#include "src/simulator.h" // for cache flushing.
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namespace v8 {
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namespace internal {
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void CpuFeatures::FlushICache(void* start, size_t size) {
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if (size == 0) return;
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if (CpuFeatures::IsSupported(COHERENT_CACHE)) return;
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#if defined(USE_SIMULATOR)
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// Not generating ARM instructions for C-code. This means that we are
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// building an ARM emulator based target. We should notify the simulator
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// that the Icache was flushed.
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// None of this code ends up in the snapshot so there are no issues
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// around whether or not to generate the code when building snapshots.
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Simulator::FlushICache(Isolate::Current()->simulator_i_cache(), start, size);
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#elif V8_OS_QNX
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msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE);
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#else
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register uint32_t beg asm("r0") = reinterpret_cast<uint32_t>(start);
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register uint32_t end asm("r1") = beg + size;
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register uint32_t flg asm("r2") = 0;
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asm volatile(
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// This assembly works for both ARM and Thumb targets.
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// Preserve r7; it is callee-saved, and GCC uses it as a frame pointer for
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// Thumb targets.
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" push {r7}\n"
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// r0 = beg
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// r1 = end
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// r2 = flags (0)
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" ldr r7, =%c[scno]\n" // r7 = syscall number
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" svc 0\n"
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" pop {r7}\n"
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:
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: "r" (beg), "r" (end), "r" (flg), [scno] "i" (__ARM_NR_cacheflush)
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: "memory");
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#endif
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}
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} } // namespace v8::internal
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#endif // V8_TARGET_ARCH_ARM
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