8804736ba3
Fixing gclient runhooks failure caused by reverted commit r23050. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/467583002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23088 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
1354 lines
39 KiB
C++
1354 lines
39 KiB
C++
// Copyright 2012 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// A Disassembler object is used to disassemble a block of code instruction by
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// instruction. The default implementation of the NameConverter object can be
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// overriden to modify register names or to do symbol lookup on addresses.
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//
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// The example below will disassemble a block of code and print it to stdout.
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//
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// NameConverter converter;
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// Disassembler d(converter);
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// for (byte* pc = begin; pc < end;) {
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// v8::internal::EmbeddedVector<char, 256> buffer;
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// byte* prev_pc = pc;
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// pc += d.InstructionDecode(buffer, pc);
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// printf("%p %08x %s\n",
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// prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer);
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// }
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//
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// The Disassembler class also has a convenience method to disassemble a block
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// of code into a FILE*, meaning that the above functionality could also be
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// achieved by just calling Disassembler::Disassemble(stdout, begin, end);
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#include <assert.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include <string.h>
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#include "src/v8.h"
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#if V8_TARGET_ARCH_MIPS
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#include "src/base/platform/platform.h"
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#include "src/disasm.h"
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#include "src/macro-assembler.h"
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#include "src/mips/constants-mips.h"
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namespace v8 {
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namespace internal {
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//------------------------------------------------------------------------------
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// Decoder decodes and disassembles instructions into an output buffer.
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// It uses the converter to convert register names and call destinations into
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// more informative description.
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class Decoder {
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public:
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Decoder(const disasm::NameConverter& converter,
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v8::internal::Vector<char> out_buffer)
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: converter_(converter),
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out_buffer_(out_buffer),
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out_buffer_pos_(0) {
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out_buffer_[out_buffer_pos_] = '\0';
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}
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~Decoder() {}
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// Writes one disassembled instruction into 'buffer' (0-terminated).
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// Returns the length of the disassembled machine instruction in bytes.
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int InstructionDecode(byte* instruction);
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private:
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// Bottleneck functions to print into the out_buffer.
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void PrintChar(const char ch);
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void Print(const char* str);
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// Printing of common values.
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void PrintRegister(int reg);
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void PrintFPURegister(int freg);
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void PrintRs(Instruction* instr);
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void PrintRt(Instruction* instr);
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void PrintRd(Instruction* instr);
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void PrintFs(Instruction* instr);
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void PrintFt(Instruction* instr);
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void PrintFd(Instruction* instr);
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void PrintSa(Instruction* instr);
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void PrintSd(Instruction* instr);
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void PrintSs1(Instruction* instr);
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void PrintSs2(Instruction* instr);
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void PrintBc(Instruction* instr);
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void PrintCc(Instruction* instr);
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void PrintFunction(Instruction* instr);
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void PrintSecondaryField(Instruction* instr);
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void PrintUImm16(Instruction* instr);
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void PrintSImm16(Instruction* instr);
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void PrintXImm16(Instruction* instr);
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void PrintXImm21(Instruction* instr);
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void PrintXImm26(Instruction* instr);
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void PrintCode(Instruction* instr); // For break and trap instructions.
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// Printing of instruction name.
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void PrintInstructionName(Instruction* instr);
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// Handle formatting of instructions and their options.
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int FormatRegister(Instruction* instr, const char* option);
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int FormatFPURegister(Instruction* instr, const char* option);
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int FormatOption(Instruction* instr, const char* option);
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void Format(Instruction* instr, const char* format);
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void Unknown(Instruction* instr);
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// Each of these functions decodes one particular instruction type.
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void DecodeTypeRegister(Instruction* instr);
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void DecodeTypeImmediate(Instruction* instr);
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void DecodeTypeJump(Instruction* instr);
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const disasm::NameConverter& converter_;
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v8::internal::Vector<char> out_buffer_;
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int out_buffer_pos_;
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DISALLOW_COPY_AND_ASSIGN(Decoder);
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};
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// Support for assertions in the Decoder formatting functions.
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#define STRING_STARTS_WITH(string, compare_string) \
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(strncmp(string, compare_string, strlen(compare_string)) == 0)
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// Append the ch to the output buffer.
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void Decoder::PrintChar(const char ch) {
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out_buffer_[out_buffer_pos_++] = ch;
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}
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// Append the str to the output buffer.
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void Decoder::Print(const char* str) {
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char cur = *str++;
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while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
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PrintChar(cur);
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cur = *str++;
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}
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out_buffer_[out_buffer_pos_] = 0;
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}
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// Print the register name according to the active name converter.
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void Decoder::PrintRegister(int reg) {
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Print(converter_.NameOfCPURegister(reg));
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}
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void Decoder::PrintRs(Instruction* instr) {
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int reg = instr->RsValue();
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PrintRegister(reg);
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}
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void Decoder::PrintRt(Instruction* instr) {
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int reg = instr->RtValue();
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PrintRegister(reg);
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}
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void Decoder::PrintRd(Instruction* instr) {
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int reg = instr->RdValue();
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PrintRegister(reg);
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}
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// Print the FPUregister name according to the active name converter.
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void Decoder::PrintFPURegister(int freg) {
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Print(converter_.NameOfXMMRegister(freg));
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}
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void Decoder::PrintFs(Instruction* instr) {
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int freg = instr->RsValue();
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PrintFPURegister(freg);
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}
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void Decoder::PrintFt(Instruction* instr) {
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int freg = instr->RtValue();
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PrintFPURegister(freg);
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}
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void Decoder::PrintFd(Instruction* instr) {
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int freg = instr->RdValue();
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PrintFPURegister(freg);
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}
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// Print the integer value of the sa field.
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void Decoder::PrintSa(Instruction* instr) {
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int sa = instr->SaValue();
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
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}
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// Print the integer value of the rd field, when it is not used as reg.
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void Decoder::PrintSd(Instruction* instr) {
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int sd = instr->RdValue();
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd);
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}
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// Print the integer value of the rd field, when used as 'ext' size.
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void Decoder::PrintSs1(Instruction* instr) {
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int ss = instr->RdValue();
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", ss + 1);
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}
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// Print the integer value of the rd field, when used as 'ins' size.
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void Decoder::PrintSs2(Instruction* instr) {
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int ss = instr->RdValue();
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int pos = instr->SaValue();
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out_buffer_pos_ +=
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SNPrintF(out_buffer_ + out_buffer_pos_, "%d", ss - pos + 1);
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}
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// Print the integer value of the cc field for the bc1t/f instructions.
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void Decoder::PrintBc(Instruction* instr) {
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int cc = instr->FBccValue();
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", cc);
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}
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// Print the integer value of the cc field for the FP compare instructions.
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void Decoder::PrintCc(Instruction* instr) {
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int cc = instr->FCccValue();
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "cc(%d)", cc);
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}
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// Print 16-bit unsigned immediate value.
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void Decoder::PrintUImm16(Instruction* instr) {
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int32_t imm = instr->Imm16Value();
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
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}
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// Print 16-bit signed immediate value.
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void Decoder::PrintSImm16(Instruction* instr) {
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int32_t imm = ((instr->Imm16Value()) << 16) >> 16;
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
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}
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// Print 16-bit hexa immediate value.
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void Decoder::PrintXImm16(Instruction* instr) {
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int32_t imm = instr->Imm16Value();
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
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}
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// Print 21-bit immediate value.
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void Decoder::PrintXImm21(Instruction* instr) {
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uint32_t imm = instr->Imm21Value();
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
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}
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// Print 26-bit immediate value.
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void Decoder::PrintXImm26(Instruction* instr) {
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uint32_t imm = instr->Imm26Value() << kImmFieldShift;
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
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}
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// Print 26-bit immediate value.
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void Decoder::PrintCode(Instruction* instr) {
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if (instr->OpcodeFieldRaw() != SPECIAL)
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return; // Not a break or trap instruction.
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switch (instr->FunctionFieldRaw()) {
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case BREAK: {
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int32_t code = instr->Bits(25, 6);
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out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
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"0x%05x (%d)", code, code);
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break;
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}
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case TGE:
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case TGEU:
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case TLT:
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case TLTU:
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case TEQ:
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case TNE: {
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int32_t code = instr->Bits(15, 6);
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out_buffer_pos_ +=
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SNPrintF(out_buffer_ + out_buffer_pos_, "0x%03x", code);
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break;
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}
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default: // Not a break or trap instruction.
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break;
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}
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}
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// Printing of instruction name.
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void Decoder::PrintInstructionName(Instruction* instr) {
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}
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// Handle all register based formatting in this function to reduce the
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// complexity of FormatOption.
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int Decoder::FormatRegister(Instruction* instr, const char* format) {
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DCHECK(format[0] == 'r');
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if (format[1] == 's') { // 'rs: Rs register.
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int reg = instr->RsValue();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 't') { // 'rt: rt register.
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int reg = instr->RtValue();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'd') { // 'rd: rd register.
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int reg = instr->RdValue();
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PrintRegister(reg);
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return 2;
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}
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UNREACHABLE();
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return -1;
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}
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// Handle all FPUregister based formatting in this function to reduce the
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// complexity of FormatOption.
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int Decoder::FormatFPURegister(Instruction* instr, const char* format) {
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DCHECK(format[0] == 'f');
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if (format[1] == 's') { // 'fs: fs register.
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int reg = instr->FsValue();
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PrintFPURegister(reg);
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return 2;
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} else if (format[1] == 't') { // 'ft: ft register.
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int reg = instr->FtValue();
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PrintFPURegister(reg);
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return 2;
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} else if (format[1] == 'd') { // 'fd: fd register.
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int reg = instr->FdValue();
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PrintFPURegister(reg);
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return 2;
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} else if (format[1] == 'r') { // 'fr: fr register.
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int reg = instr->FrValue();
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PrintFPURegister(reg);
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return 2;
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}
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UNREACHABLE();
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return -1;
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}
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// FormatOption takes a formatting string and interprets it based on
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// the current instructions. The format string points to the first
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// character of the option string (the option escape has already been
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// consumed by the caller.) FormatOption returns the number of
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// characters that were consumed from the formatting string.
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int Decoder::FormatOption(Instruction* instr, const char* format) {
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switch (format[0]) {
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case 'c': { // 'code for break or trap instructions.
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DCHECK(STRING_STARTS_WITH(format, "code"));
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PrintCode(instr);
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return 4;
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}
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case 'i': { // 'imm16u or 'imm26.
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if (format[3] == '1') {
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DCHECK(STRING_STARTS_WITH(format, "imm16"));
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if (format[5] == 's') {
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DCHECK(STRING_STARTS_WITH(format, "imm16s"));
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PrintSImm16(instr);
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} else if (format[5] == 'u') {
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DCHECK(STRING_STARTS_WITH(format, "imm16u"));
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PrintSImm16(instr);
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} else {
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DCHECK(STRING_STARTS_WITH(format, "imm16x"));
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PrintXImm16(instr);
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}
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return 6;
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} else if (format[3] == '2' && format[4] == '1') {
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DCHECK(STRING_STARTS_WITH(format, "imm21x"));
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PrintXImm21(instr);
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return 6;
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} else if (format[3] == '2' && format[4] == '6') {
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DCHECK(STRING_STARTS_WITH(format, "imm26x"));
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PrintXImm26(instr);
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return 6;
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}
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}
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case 'r': { // 'r: registers.
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return FormatRegister(instr, format);
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}
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case 'f': { // 'f: FPUregisters.
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return FormatFPURegister(instr, format);
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}
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case 's': { // 'sa.
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switch (format[1]) {
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case 'a': {
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DCHECK(STRING_STARTS_WITH(format, "sa"));
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PrintSa(instr);
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return 2;
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}
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case 'd': {
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DCHECK(STRING_STARTS_WITH(format, "sd"));
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PrintSd(instr);
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return 2;
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}
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case 's': {
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if (format[2] == '1') {
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DCHECK(STRING_STARTS_WITH(format, "ss1")); /* ext size */
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PrintSs1(instr);
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return 3;
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} else {
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DCHECK(STRING_STARTS_WITH(format, "ss2")); /* ins size */
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PrintSs2(instr);
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return 3;
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}
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}
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}
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}
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case 'b': { // 'bc - Special for bc1 cc field.
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DCHECK(STRING_STARTS_WITH(format, "bc"));
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PrintBc(instr);
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return 2;
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}
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case 'C': { // 'Cc - Special for c.xx.d cc field.
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DCHECK(STRING_STARTS_WITH(format, "Cc"));
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PrintCc(instr);
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return 2;
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}
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}
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UNREACHABLE();
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return -1;
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}
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// Format takes a formatting string for a whole instruction and prints it into
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// the output buffer. All escaped options are handed to FormatOption to be
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// parsed further.
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void Decoder::Format(Instruction* instr, const char* format) {
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char cur = *format++;
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while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
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if (cur == '\'') { // Single quote is used as the formatting escape.
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format += FormatOption(instr, format);
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} else {
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out_buffer_[out_buffer_pos_++] = cur;
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}
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cur = *format++;
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}
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out_buffer_[out_buffer_pos_] = '\0';
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}
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// For currently unimplemented decodings the disassembler calls Unknown(instr)
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// which will just print "unknown" of the instruction bits.
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void Decoder::Unknown(Instruction* instr) {
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Format(instr, "unknown");
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}
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void Decoder::DecodeTypeRegister(Instruction* instr) {
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switch (instr->OpcodeFieldRaw()) {
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case COP1: // Coprocessor instructions.
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switch (instr->RsFieldRaw()) {
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case BC1: // bc1 handled in DecodeTypeImmediate.
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UNREACHABLE();
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break;
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case MFC1:
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Format(instr, "mfc1 'rt, 'fs");
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break;
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case MFHC1:
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Format(instr, "mfhc1 'rt, 'fs");
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break;
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case MTC1:
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Format(instr, "mtc1 'rt, 'fs");
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break;
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// These are called "fs" too, although they are not FPU registers.
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case CTC1:
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Format(instr, "ctc1 'rt, 'fs");
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break;
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case CFC1:
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Format(instr, "cfc1 'rt, 'fs");
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break;
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case MTHC1:
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Format(instr, "mthc1 'rt, 'fs");
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break;
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case D:
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switch (instr->FunctionFieldRaw()) {
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case ADD_D:
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Format(instr, "add.d 'fd, 'fs, 'ft");
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break;
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case SUB_D:
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Format(instr, "sub.d 'fd, 'fs, 'ft");
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break;
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case MUL_D:
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Format(instr, "mul.d 'fd, 'fs, 'ft");
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break;
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case DIV_D:
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Format(instr, "div.d 'fd, 'fs, 'ft");
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break;
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case ABS_D:
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Format(instr, "abs.d 'fd, 'fs");
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break;
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case MOV_D:
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Format(instr, "mov.d 'fd, 'fs");
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break;
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case NEG_D:
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Format(instr, "neg.d 'fd, 'fs");
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break;
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case SQRT_D:
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Format(instr, "sqrt.d 'fd, 'fs");
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break;
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case CVT_W_D:
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Format(instr, "cvt.w.d 'fd, 'fs");
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break;
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case CVT_L_D:
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Format(instr, "cvt.l.d 'fd, 'fs");
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break;
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case TRUNC_W_D:
|
|
Format(instr, "trunc.w.d 'fd, 'fs");
|
|
break;
|
|
case TRUNC_L_D:
|
|
Format(instr, "trunc.l.d 'fd, 'fs");
|
|
break;
|
|
case ROUND_W_D:
|
|
Format(instr, "round.w.d 'fd, 'fs");
|
|
break;
|
|
case FLOOR_W_D:
|
|
Format(instr, "floor.w.d 'fd, 'fs");
|
|
break;
|
|
case CEIL_W_D:
|
|
Format(instr, "ceil.w.d 'fd, 'fs");
|
|
break;
|
|
case CVT_S_D:
|
|
Format(instr, "cvt.s.d 'fd, 'fs");
|
|
break;
|
|
case C_F_D:
|
|
Format(instr, "c.f.d 'fs, 'ft, 'Cc");
|
|
break;
|
|
case C_UN_D:
|
|
Format(instr, "c.un.d 'fs, 'ft, 'Cc");
|
|
break;
|
|
case C_EQ_D:
|
|
Format(instr, "c.eq.d 'fs, 'ft, 'Cc");
|
|
break;
|
|
case C_UEQ_D:
|
|
Format(instr, "c.ueq.d 'fs, 'ft, 'Cc");
|
|
break;
|
|
case C_OLT_D:
|
|
Format(instr, "c.olt.d 'fs, 'ft, 'Cc");
|
|
break;
|
|
case C_ULT_D:
|
|
Format(instr, "c.ult.d 'fs, 'ft, 'Cc");
|
|
break;
|
|
case C_OLE_D:
|
|
Format(instr, "c.ole.d 'fs, 'ft, 'Cc");
|
|
break;
|
|
case C_ULE_D:
|
|
Format(instr, "c.ule.d 'fs, 'ft, 'Cc");
|
|
break;
|
|
default:
|
|
Format(instr, "unknown.cop1.d");
|
|
break;
|
|
}
|
|
break;
|
|
case S:
|
|
UNIMPLEMENTED_MIPS();
|
|
break;
|
|
case W:
|
|
switch (instr->FunctionFieldRaw()) {
|
|
case CVT_S_W: // Convert word to float (single).
|
|
Format(instr, "cvt.s.w 'fd, 'fs");
|
|
break;
|
|
case CVT_D_W: // Convert word to double.
|
|
Format(instr, "cvt.d.w 'fd, 'fs");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case L:
|
|
switch (instr->FunctionFieldRaw()) {
|
|
case CVT_D_L:
|
|
Format(instr, "cvt.d.l 'fd, 'fs");
|
|
break;
|
|
case CVT_S_L:
|
|
Format(instr, "cvt.s.l 'fd, 'fs");
|
|
break;
|
|
case CMP_UN:
|
|
Format(instr, "cmp.un.d 'fd, 'fs, 'ft");
|
|
break;
|
|
case CMP_EQ:
|
|
Format(instr, "cmp.eq.d 'fd, 'fs, 'ft");
|
|
break;
|
|
case CMP_UEQ:
|
|
Format(instr, "cmp.ueq.d 'fd, 'fs, 'ft");
|
|
break;
|
|
case CMP_LT:
|
|
Format(instr, "cmp.lt.d 'fd, 'fs, 'ft");
|
|
break;
|
|
case CMP_ULT:
|
|
Format(instr, "cmp.ult.d 'fd, 'fs, 'ft");
|
|
break;
|
|
case CMP_LE:
|
|
Format(instr, "cmp.le.d 'fd, 'fs, 'ft");
|
|
break;
|
|
case CMP_ULE:
|
|
Format(instr, "cmp.ule.d 'fd, 'fs, 'ft");
|
|
break;
|
|
case CMP_OR:
|
|
Format(instr, "cmp.or.d 'fd, 'fs, 'ft");
|
|
break;
|
|
case CMP_UNE:
|
|
Format(instr, "cmp.une.d 'fd, 'fs, 'ft");
|
|
break;
|
|
case CMP_NE:
|
|
Format(instr, "cmp.ne.d 'fd, 'fs, 'ft");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case PS:
|
|
UNIMPLEMENTED_MIPS();
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case COP1X:
|
|
switch (instr->FunctionFieldRaw()) {
|
|
case MADD_D:
|
|
Format(instr, "madd.d 'fd, 'fr, 'fs, 'ft");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case SPECIAL:
|
|
switch (instr->FunctionFieldRaw()) {
|
|
case JR:
|
|
Format(instr, "jr 'rs");
|
|
break;
|
|
case JALR:
|
|
Format(instr, "jalr 'rs");
|
|
break;
|
|
case SLL:
|
|
if ( 0x0 == static_cast<int>(instr->InstructionBits()))
|
|
Format(instr, "nop");
|
|
else
|
|
Format(instr, "sll 'rd, 'rt, 'sa");
|
|
break;
|
|
case SRL:
|
|
if (instr->RsValue() == 0) {
|
|
Format(instr, "srl 'rd, 'rt, 'sa");
|
|
} else {
|
|
if (IsMipsArchVariant(kMips32r2)) {
|
|
Format(instr, "rotr 'rd, 'rt, 'sa");
|
|
} else {
|
|
Unknown(instr);
|
|
}
|
|
}
|
|
break;
|
|
case SRA:
|
|
Format(instr, "sra 'rd, 'rt, 'sa");
|
|
break;
|
|
case SLLV:
|
|
Format(instr, "sllv 'rd, 'rt, 'rs");
|
|
break;
|
|
case SRLV:
|
|
if (instr->SaValue() == 0) {
|
|
Format(instr, "srlv 'rd, 'rt, 'rs");
|
|
} else {
|
|
if (IsMipsArchVariant(kMips32r2)) {
|
|
Format(instr, "rotrv 'rd, 'rt, 'rs");
|
|
} else {
|
|
Unknown(instr);
|
|
}
|
|
}
|
|
break;
|
|
case SRAV:
|
|
Format(instr, "srav 'rd, 'rt, 'rs");
|
|
break;
|
|
case MFHI:
|
|
if (instr->Bits(25, 16) == 0) {
|
|
Format(instr, "mfhi 'rd");
|
|
} else {
|
|
if ((instr->FunctionFieldRaw() == CLZ_R6)
|
|
&& (instr->FdValue() == 1)) {
|
|
Format(instr, "clz 'rd, 'rs");
|
|
} else if ((instr->FunctionFieldRaw() == CLO_R6)
|
|
&& (instr->FdValue() == 1)) {
|
|
Format(instr, "clo 'rd, 'rs");
|
|
}
|
|
}
|
|
break;
|
|
case MFLO:
|
|
Format(instr, "mflo 'rd");
|
|
break;
|
|
case MULT: // @Mips32r6 == MUL_MUH.
|
|
if (!IsMipsArchVariant(kMips32r6)) {
|
|
Format(instr, "mult 'rs, 'rt");
|
|
} else {
|
|
if (instr->SaValue() == MUL_OP) {
|
|
Format(instr, "mul 'rd, 'rs, 'rt");
|
|
} else {
|
|
Format(instr, "muh 'rd, 'rs, 'rt");
|
|
}
|
|
}
|
|
break;
|
|
case MULTU: // @Mips32r6 == MUL_MUH_U.
|
|
if (!IsMipsArchVariant(kMips32r6)) {
|
|
Format(instr, "multu 'rs, 'rt");
|
|
} else {
|
|
if (instr->SaValue() == MUL_OP) {
|
|
Format(instr, "mulu 'rd, 'rs, 'rt");
|
|
} else {
|
|
Format(instr, "muhu 'rd, 'rs, 'rt");
|
|
}
|
|
}
|
|
break;
|
|
case DIV: // @Mips32r6 == DIV_MOD.
|
|
if (!IsMipsArchVariant(kMips32r6)) {
|
|
Format(instr, "div 'rs, 'rt");
|
|
} else {
|
|
if (instr->SaValue() == DIV_OP) {
|
|
Format(instr, "div 'rd, 'rs, 'rt");
|
|
} else {
|
|
Format(instr, "mod 'rd, 'rs, 'rt");
|
|
}
|
|
}
|
|
break;
|
|
case DIVU: // @Mips32r6 == DIV_MOD_U.
|
|
if (!IsMipsArchVariant(kMips32r6)) {
|
|
Format(instr, "divu 'rs, 'rt");
|
|
} else {
|
|
if (instr->SaValue() == DIV_OP) {
|
|
Format(instr, "divu 'rd, 'rs, 'rt");
|
|
} else {
|
|
Format(instr, "modu 'rd, 'rs, 'rt");
|
|
}
|
|
}
|
|
break;
|
|
case ADD:
|
|
Format(instr, "add 'rd, 'rs, 'rt");
|
|
break;
|
|
case ADDU:
|
|
Format(instr, "addu 'rd, 'rs, 'rt");
|
|
break;
|
|
case SUB:
|
|
Format(instr, "sub 'rd, 'rs, 'rt");
|
|
break;
|
|
case SUBU:
|
|
Format(instr, "subu 'rd, 'rs, 'rt");
|
|
break;
|
|
case AND:
|
|
Format(instr, "and 'rd, 'rs, 'rt");
|
|
break;
|
|
case OR:
|
|
if (0 == instr->RsValue()) {
|
|
Format(instr, "mov 'rd, 'rt");
|
|
} else if (0 == instr->RtValue()) {
|
|
Format(instr, "mov 'rd, 'rs");
|
|
} else {
|
|
Format(instr, "or 'rd, 'rs, 'rt");
|
|
}
|
|
break;
|
|
case XOR:
|
|
Format(instr, "xor 'rd, 'rs, 'rt");
|
|
break;
|
|
case NOR:
|
|
Format(instr, "nor 'rd, 'rs, 'rt");
|
|
break;
|
|
case SLT:
|
|
Format(instr, "slt 'rd, 'rs, 'rt");
|
|
break;
|
|
case SLTU:
|
|
Format(instr, "sltu 'rd, 'rs, 'rt");
|
|
break;
|
|
case BREAK:
|
|
Format(instr, "break, code: 'code");
|
|
break;
|
|
case TGE:
|
|
Format(instr, "tge 'rs, 'rt, code: 'code");
|
|
break;
|
|
case TGEU:
|
|
Format(instr, "tgeu 'rs, 'rt, code: 'code");
|
|
break;
|
|
case TLT:
|
|
Format(instr, "tlt 'rs, 'rt, code: 'code");
|
|
break;
|
|
case TLTU:
|
|
Format(instr, "tltu 'rs, 'rt, code: 'code");
|
|
break;
|
|
case TEQ:
|
|
Format(instr, "teq 'rs, 'rt, code: 'code");
|
|
break;
|
|
case TNE:
|
|
Format(instr, "tne 'rs, 'rt, code: 'code");
|
|
break;
|
|
case MOVZ:
|
|
Format(instr, "movz 'rd, 'rs, 'rt");
|
|
break;
|
|
case MOVN:
|
|
Format(instr, "movn 'rd, 'rs, 'rt");
|
|
break;
|
|
case MOVCI:
|
|
if (instr->Bit(16)) {
|
|
Format(instr, "movt 'rd, 'rs, 'bc");
|
|
} else {
|
|
Format(instr, "movf 'rd, 'rs, 'bc");
|
|
}
|
|
break;
|
|
case SELEQZ_S:
|
|
Format(instr, "seleqz 'rd, 'rs, 'rt");
|
|
break;
|
|
case SELNEZ_S:
|
|
Format(instr, "selnez 'rd, 'rs, 'rt");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case SPECIAL2:
|
|
switch (instr->FunctionFieldRaw()) {
|
|
case MUL:
|
|
Format(instr, "mul 'rd, 'rs, 'rt");
|
|
break;
|
|
case CLZ:
|
|
if (!IsMipsArchVariant(kMips32r6)) {
|
|
Format(instr, "clz 'rd, 'rs");
|
|
}
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case SPECIAL3:
|
|
switch (instr->FunctionFieldRaw()) {
|
|
case INS: {
|
|
if (IsMipsArchVariant(kMips32r2)) {
|
|
Format(instr, "ins 'rt, 'rs, 'sa, 'ss2");
|
|
} else {
|
|
Unknown(instr);
|
|
}
|
|
break;
|
|
}
|
|
case EXT: {
|
|
if (IsMipsArchVariant(kMips32r2)) {
|
|
Format(instr, "ext 'rt, 'rs, 'sa, 'ss1");
|
|
} else {
|
|
Unknown(instr);
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeTypeImmediate(Instruction* instr) {
|
|
switch (instr->OpcodeFieldRaw()) {
|
|
case COP1:
|
|
switch (instr->RsFieldRaw()) {
|
|
case BC1:
|
|
if (instr->FBtrueValue()) {
|
|
Format(instr, "bc1t 'bc, 'imm16u");
|
|
} else {
|
|
Format(instr, "bc1f 'bc, 'imm16u");
|
|
}
|
|
break;
|
|
case BC1EQZ:
|
|
Format(instr, "bc1eqz 'ft, 'imm16u");
|
|
break;
|
|
case BC1NEZ:
|
|
Format(instr, "bc1nez 'ft, 'imm16u");
|
|
break;
|
|
case W: // CMP.S instruction.
|
|
switch (instr->FunctionValue()) {
|
|
case CMP_AF:
|
|
Format(instr, "cmp.af.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_UN:
|
|
Format(instr, "cmp.un.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_EQ:
|
|
Format(instr, "cmp.eq.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_UEQ:
|
|
Format(instr, "cmp.ueq.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_LT:
|
|
Format(instr, "cmp.lt.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_ULT:
|
|
Format(instr, "cmp.ult.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_LE:
|
|
Format(instr, "cmp.le.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_ULE:
|
|
Format(instr, "cmp.ule.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_OR:
|
|
Format(instr, "cmp.or.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_UNE:
|
|
Format(instr, "cmp.une.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_NE:
|
|
Format(instr, "cmp.ne.S 'ft, 'fs, 'fd");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case L: // CMP.D instruction.
|
|
switch (instr->FunctionValue()) {
|
|
case CMP_AF:
|
|
Format(instr, "cmp.af.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_UN:
|
|
Format(instr, "cmp.un.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_EQ:
|
|
Format(instr, "cmp.eq.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_UEQ:
|
|
Format(instr, "cmp.ueq.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_LT:
|
|
Format(instr, "cmp.lt.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_ULT:
|
|
Format(instr, "cmp.ult.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_LE:
|
|
Format(instr, "cmp.le.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_ULE:
|
|
Format(instr, "cmp.ule.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_OR:
|
|
Format(instr, "cmp.or.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_UNE:
|
|
Format(instr, "cmp.une.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case CMP_NE:
|
|
Format(instr, "cmp.ne.D 'ft, 'fs, 'fd");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case S:
|
|
switch (instr->FunctionValue()) {
|
|
case SEL:
|
|
Format(instr, "sel.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case SELEQZ_C:
|
|
Format(instr, "seleqz.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case SELNEZ_C:
|
|
Format(instr, "selnez.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case MIN:
|
|
Format(instr, "min.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case MINA:
|
|
Format(instr, "mina.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case MAX:
|
|
Format(instr, "max.S 'ft, 'fs, 'fd");
|
|
break;
|
|
case MAXA:
|
|
Format(instr, "maxa.S 'ft, 'fs, 'fd");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case D:
|
|
switch (instr->FunctionValue()) {
|
|
case SEL:
|
|
Format(instr, "sel.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case SELEQZ_C:
|
|
Format(instr, "seleqz.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case SELNEZ_C:
|
|
Format(instr, "selnez.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case MIN:
|
|
Format(instr, "min.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case MINA:
|
|
Format(instr, "mina.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case MAX:
|
|
Format(instr, "max.D 'ft, 'fs, 'fd");
|
|
break;
|
|
case MAXA:
|
|
Format(instr, "maxa.D 'ft, 'fs, 'fd");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
|
|
break; // Case COP1.
|
|
// ------------- REGIMM class.
|
|
case REGIMM:
|
|
switch (instr->RtFieldRaw()) {
|
|
case BLTZ:
|
|
Format(instr, "bltz 'rs, 'imm16u");
|
|
break;
|
|
case BLTZAL:
|
|
Format(instr, "bltzal 'rs, 'imm16u");
|
|
break;
|
|
case BGEZ:
|
|
Format(instr, "bgez 'rs, 'imm16u");
|
|
break;
|
|
case BGEZAL:
|
|
Format(instr, "bgezal 'rs, 'imm16u");
|
|
break;
|
|
case BGEZALL:
|
|
Format(instr, "bgezall 'rs, 'imm16u");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
break; // Case REGIMM.
|
|
// ------------- Branch instructions.
|
|
case BEQ:
|
|
Format(instr, "beq 'rs, 'rt, 'imm16u");
|
|
break;
|
|
case BNE:
|
|
Format(instr, "bne 'rs, 'rt, 'imm16u");
|
|
break;
|
|
case BLEZ:
|
|
if ((instr->RtFieldRaw() == 0)
|
|
&& (instr->RsFieldRaw() != 0)) {
|
|
Format(instr, "blez 'rs, 'imm16u");
|
|
} else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
|
|
&& (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bgeuc 'rs, 'rt, 'imm16u");
|
|
} else if ((instr->RtFieldRaw() == instr->RsFieldRaw())
|
|
&& (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bgezalc 'rs, 'imm16u");
|
|
} else if ((instr->RsFieldRaw() == 0)
|
|
&& (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "blezalc 'rs, 'imm16u");
|
|
} else {
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case BGTZ:
|
|
if ((instr->RtFieldRaw() == 0)
|
|
&& (instr->RsFieldRaw() != 0)) {
|
|
Format(instr, "bgtz 'rs, 'imm16u");
|
|
} else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
|
|
&& (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bltuc 'rs, 'rt, 'imm16u");
|
|
} else if ((instr->RtFieldRaw() == instr->RsFieldRaw())
|
|
&& (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bltzalc 'rt, 'imm16u");
|
|
} else if ((instr->RsFieldRaw() == 0)
|
|
&& (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bgtzalc 'rt, 'imm16u");
|
|
} else {
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case BLEZL:
|
|
if ((instr->RtFieldRaw() == instr->RsFieldRaw())
|
|
&& (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bgezc 'rt, 'imm16u");
|
|
} else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
|
|
&& (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bgec 'rs, 'rt, 'imm16u");
|
|
} else if ((instr->RsFieldRaw() == 0)
|
|
&& (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "blezc 'rt, 'imm16u");
|
|
} else {
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case BGTZL:
|
|
if ((instr->RtFieldRaw() == instr->RsFieldRaw())
|
|
&& (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bltzc 'rt, 'imm16u");
|
|
} else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
|
|
&& (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bltc 'rs, 'rt, 'imm16u");
|
|
} else if ((instr->RsFieldRaw() == 0)
|
|
&& (instr->RtFieldRaw() != 0)) {
|
|
Format(instr, "bgtzc 'rt, 'imm16u");
|
|
} else {
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
case BEQZC:
|
|
if (instr->RsFieldRaw() != 0) {
|
|
Format(instr, "beqzc 'rs, 'imm21x");
|
|
}
|
|
break;
|
|
case BNEZC:
|
|
if (instr->RsFieldRaw() != 0) {
|
|
Format(instr, "bnezc 'rs, 'imm21x");
|
|
}
|
|
break;
|
|
// ------------- Arithmetic instructions.
|
|
case ADDI:
|
|
if (!IsMipsArchVariant(kMips32r6)) {
|
|
Format(instr, "addi 'rt, 'rs, 'imm16s");
|
|
} else {
|
|
// Check if BOVC or BEQC instruction.
|
|
if (instr->RsFieldRaw() >= instr->RtFieldRaw()) {
|
|
Format(instr, "bovc 'rs, 'rt, 'imm16s");
|
|
} else if (instr->RsFieldRaw() < instr->RtFieldRaw()) {
|
|
Format(instr, "beqc 'rs, 'rt, 'imm16s");
|
|
} else {
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
break;
|
|
case DADDI:
|
|
if (IsMipsArchVariant(kMips32r6)) {
|
|
// Check if BNVC or BNEC instruction.
|
|
if (instr->RsFieldRaw() >= instr->RtFieldRaw()) {
|
|
Format(instr, "bnvc 'rs, 'rt, 'imm16s");
|
|
} else if (instr->RsFieldRaw() < instr->RtFieldRaw()) {
|
|
Format(instr, "bnec 'rs, 'rt, 'imm16s");
|
|
} else {
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
break;
|
|
case ADDIU:
|
|
Format(instr, "addiu 'rt, 'rs, 'imm16s");
|
|
break;
|
|
case SLTI:
|
|
Format(instr, "slti 'rt, 'rs, 'imm16s");
|
|
break;
|
|
case SLTIU:
|
|
Format(instr, "sltiu 'rt, 'rs, 'imm16u");
|
|
break;
|
|
case ANDI:
|
|
Format(instr, "andi 'rt, 'rs, 'imm16x");
|
|
break;
|
|
case ORI:
|
|
Format(instr, "ori 'rt, 'rs, 'imm16x");
|
|
break;
|
|
case XORI:
|
|
Format(instr, "xori 'rt, 'rs, 'imm16x");
|
|
break;
|
|
case LUI:
|
|
if (!IsMipsArchVariant(kMips32r6)) {
|
|
Format(instr, "lui 'rt, 'imm16x");
|
|
} else {
|
|
if (instr->RsValue() != 0) {
|
|
Format(instr, "aui 'rt, 'imm16x");
|
|
} else {
|
|
Format(instr, "lui 'rt, 'imm16x");
|
|
}
|
|
}
|
|
break;
|
|
// ------------- Memory instructions.
|
|
case LB:
|
|
Format(instr, "lb 'rt, 'imm16s('rs)");
|
|
break;
|
|
case LH:
|
|
Format(instr, "lh 'rt, 'imm16s('rs)");
|
|
break;
|
|
case LWL:
|
|
Format(instr, "lwl 'rt, 'imm16s('rs)");
|
|
break;
|
|
case LW:
|
|
Format(instr, "lw 'rt, 'imm16s('rs)");
|
|
break;
|
|
case LBU:
|
|
Format(instr, "lbu 'rt, 'imm16s('rs)");
|
|
break;
|
|
case LHU:
|
|
Format(instr, "lhu 'rt, 'imm16s('rs)");
|
|
break;
|
|
case LWR:
|
|
Format(instr, "lwr 'rt, 'imm16s('rs)");
|
|
break;
|
|
case PREF:
|
|
Format(instr, "pref 'rt, 'imm16s('rs)");
|
|
break;
|
|
case SB:
|
|
Format(instr, "sb 'rt, 'imm16s('rs)");
|
|
break;
|
|
case SH:
|
|
Format(instr, "sh 'rt, 'imm16s('rs)");
|
|
break;
|
|
case SWL:
|
|
Format(instr, "swl 'rt, 'imm16s('rs)");
|
|
break;
|
|
case SW:
|
|
Format(instr, "sw 'rt, 'imm16s('rs)");
|
|
break;
|
|
case SWR:
|
|
Format(instr, "swr 'rt, 'imm16s('rs)");
|
|
break;
|
|
case LWC1:
|
|
Format(instr, "lwc1 'ft, 'imm16s('rs)");
|
|
break;
|
|
case LDC1:
|
|
Format(instr, "ldc1 'ft, 'imm16s('rs)");
|
|
break;
|
|
case SWC1:
|
|
Format(instr, "swc1 'ft, 'imm16s('rs)");
|
|
break;
|
|
case SDC1:
|
|
Format(instr, "sdc1 'ft, 'imm16s('rs)");
|
|
break;
|
|
default:
|
|
printf("a 0x%x \n", instr->OpcodeFieldRaw());
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeTypeJump(Instruction* instr) {
|
|
switch (instr->OpcodeFieldRaw()) {
|
|
case J:
|
|
Format(instr, "j 'imm26x");
|
|
break;
|
|
case JAL:
|
|
Format(instr, "jal 'imm26x");
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
|
|
|
|
// Disassemble the instruction at *instr_ptr into the output buffer.
|
|
int Decoder::InstructionDecode(byte* instr_ptr) {
|
|
Instruction* instr = Instruction::At(instr_ptr);
|
|
// Print raw instruction bytes.
|
|
out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
|
|
"%08x ",
|
|
instr->InstructionBits());
|
|
switch (instr->InstructionType()) {
|
|
case Instruction::kRegisterType: {
|
|
DecodeTypeRegister(instr);
|
|
break;
|
|
}
|
|
case Instruction::kImmediateType: {
|
|
DecodeTypeImmediate(instr);
|
|
break;
|
|
}
|
|
case Instruction::kJumpType: {
|
|
DecodeTypeJump(instr);
|
|
break;
|
|
}
|
|
default: {
|
|
Format(instr, "UNSUPPORTED");
|
|
UNSUPPORTED_MIPS();
|
|
}
|
|
}
|
|
return Instruction::kInstrSize;
|
|
}
|
|
|
|
|
|
} } // namespace v8::internal
|
|
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
namespace disasm {
|
|
|
|
const char* NameConverter::NameOfAddress(byte* addr) const {
|
|
v8::internal::SNPrintF(tmp_buffer_, "%p", addr);
|
|
return tmp_buffer_.start();
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameOfConstant(byte* addr) const {
|
|
return NameOfAddress(addr);
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameOfCPURegister(int reg) const {
|
|
return v8::internal::Registers::Name(reg);
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameOfXMMRegister(int reg) const {
|
|
return v8::internal::FPURegisters::Name(reg);
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameOfByteCPURegister(int reg) const {
|
|
UNREACHABLE(); // MIPS does not have the concept of a byte register.
|
|
return "nobytereg";
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameInCode(byte* addr) const {
|
|
// The default name converter is called for unknown code. So we will not try
|
|
// to access any memory.
|
|
return "";
|
|
}
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
Disassembler::Disassembler(const NameConverter& converter)
|
|
: converter_(converter) {}
|
|
|
|
|
|
Disassembler::~Disassembler() {}
|
|
|
|
|
|
int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
|
|
byte* instruction) {
|
|
v8::internal::Decoder d(converter_, buffer);
|
|
return d.InstructionDecode(instruction);
|
|
}
|
|
|
|
|
|
// The MIPS assembler does not currently use constant pools.
|
|
int Disassembler::ConstantPoolSizeAt(byte* instruction) {
|
|
return -1;
|
|
}
|
|
|
|
|
|
void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
|
|
NameConverter converter;
|
|
Disassembler d(converter);
|
|
for (byte* pc = begin; pc < end;) {
|
|
v8::internal::EmbeddedVector<char, 128> buffer;
|
|
buffer[0] = '\0';
|
|
byte* prev_pc = pc;
|
|
pc += d.InstructionDecode(buffer, pc);
|
|
v8::internal::PrintF(f, "%p %08x %s\n",
|
|
prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
|
|
}
|
|
}
|
|
|
|
|
|
#undef UNSUPPORTED
|
|
|
|
} // namespace disasm
|
|
|
|
#endif // V8_TARGET_ARCH_MIPS
|