v8/test
Pierre Langlois 3f1a59f47f [arm][arm64] Do not allocate temp registers for the write barrier.
Improve code generation for stores with write barriers slightly by using the
assembler's dedicated scratch registers (x16 and x17 on Arm64, ip on Arm)
instead of allocating temporaries.

To do this, we've done two things:

  - Use ip as a scratch register when loading page flags.

  - TurboAssembler::CallRecordWriteStub() now takes the offset of the slot
    that's written to rather than its address, removing the need to allocate a
    temporary register for it.

In essence, we've gone from:

```
;; Do the store.
stur x19, [x9, #15]
;; Check *destination* object page flags and jump out-of-line.
and x4, x9, #0xfffffffffff80000
ldr x4, [x4, #8]
tbnz x4, #2, #+0x1e7c
|     ;; Check *source* object page flags.
| `-> and x4, x19, #0xfffffffffff80000
|     ldr x4, [xM, #8]
|,--- tbz x4, #1, #-0x1e80
|     ;; Compute address of slot.
|     add x5, x9, #0xf (15)
|     ;; Setup arguments to RecordWrite
|     stp x2, x3, [sp, #-32]!
|     stp x4, lr, [sp, #16]
|     stp x0, x1, [sp, #-16]!
|     mov x0, x9 ;; Object address in x9
|     mov x1, x5 ;; Slot address in x5
|     movz x2, #0x0
|     movz x3, #0x100000000
|     ;; Call RecordWrite
|     ldr x16, pc+2056
|     blr x16
```

Which allocates x4 and x5 as temporaries.

To:

```
stur x19, [x9, #15]
and x16, x9, #0xfffffffffff80000 ;; Using x16 instead of allocating x4.
ldr x16, [x16, #8]
tbnz x16, #2, #+0x1e7c
| `-> and x16, x19, #0xfffffffffff80000
|     ldr x16, [xM, #8]
|,--- tbz x16, #1, #-0x1e80
|     stp x2, x3, [sp, #-32]!
|     stp x4, lr, [sp, #16]
|     stp x0, x1, [sp, #-16]!
|     mov x0, x9            ;; Object address still in x9.
|     add x1, x9, #0xf (15) ;; Compute the slot address directly.
|     movz x2, #0x0
|     movz x3, #0x100000000
|     ldr x16, pc+2056
|     blr x16
```

Finally, `RecordWriteField()` does not need an extra scratch register anymore.

Change-Id: Icb71310e7b8ab1ca83ced250851456166b337d00
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1505793
Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
Reviewed-by: Sigurd Schneider <sigurds@chromium.org>
Reviewed-by: Ulan Degenbaev <ulan@chromium.org>
Cr-Commit-Position: refs/heads/master@{#61153}
2019-05-02 11:19:00 +00:00
..
benchmarks [test] Mark more slow tests 2019-04-26 11:51:21 +00:00
cctest [test] Stress wasm code gc in "stress_background_compile" 2019-05-02 09:56:05 +00:00
common [wasm-hints] Add Tests for Compilation Hints 2019-04-18 10:34:42 +00:00
debugger [Test] Add PrepareForOptimization to debugger/ tests. 2019-04-29 13:47:16 +00:00
fuzzer [cleanup] Use Vector::begin instead of Vector::start 2019-04-29 12:43:16 +00:00
inspector [cleanup] Use Vector::begin instead of Vector::start 2019-04-29 12:43:16 +00:00
intl Update V8 DEPS. 2019-05-02 08:30:40 +00:00
js-perf-test [Test] Add %PrepareForOptimization in tests 2019-04-30 14:18:22 +00:00
memory [snapshot] Remove the builtins snapshot 2018-10-31 10:18:28 +00:00
message [class] Remove flags for class fields 2019-05-01 02:02:51 +00:00
mjsunit [Test] Add %PrepareForOptimization in tests 2019-05-02 09:43:17 +00:00
mkgrokdump Revert "[heap] Skip ro-space from heap iterators, add CombinedHeapIterator." 2019-04-12 16:38:00 +00:00
mozilla [test] Mark more slow tests 2019-04-26 11:51:21 +00:00
preparser [test] Don't test jitless without embedded-builtins 2019-02-26 14:33:01 +00:00
test262 [Intl] Add feature mapping for Intl.DateTimeFormat-formatRange 2019-05-02 02:57:00 +00:00
torque [torque] add references to HeapObject fields. 2019-04-11 14:11:18 +00:00
unittests [arm][arm64] Do not allocate temp registers for the write barrier. 2019-05-02 11:19:00 +00:00
wasm-js [testrunner] handle timeout param in file 2019-02-27 17:49:17 +00:00
wasm-spec-tests [wasm] Update spec tests 2019-04-29 08:03:46 +00:00
webkit [test] Stress wasm code gc in "stress_background_compile" 2019-05-02 09:56:05 +00:00
BUILD.gn [cctest] Enable shared linking for cctest 2019-04-09 12:12:19 +00:00
OWNERS Make tmrts an infra OWNER 2019-02-15 09:02:24 +00:00