53340b2624
Zhang Kun. For now we only emit movw and movt in places where no relocation is needed. Small performance boost (around 0.5%). Also adds support for turning ALU operations (eor etc.) with large immediates into mvn or movw followed by a register-based ALU operation. Review URL: http://codereview.chromium.org/2821014 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
404 lines
14 KiB
C++
404 lines
14 KiB
C++
// Copyright 2007-2008 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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#include <stdlib.h>
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#include "v8.h"
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#include "debug.h"
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#include "disasm.h"
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#include "disassembler.h"
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#include "macro-assembler.h"
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#include "serialize.h"
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#include "cctest.h"
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using namespace v8::internal;
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static v8::Persistent<v8::Context> env;
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static void InitializeVM() {
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if (env.IsEmpty()) {
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env = v8::Context::New();
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}
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}
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bool DisassembleAndCompare(byte* pc, const char* compare_string) {
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disasm::NameConverter converter;
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disasm::Disassembler disasm(converter);
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EmbeddedVector<char, 128> disasm_buffer;
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disasm.InstructionDecode(disasm_buffer, pc);
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if (strcmp(compare_string, disasm_buffer.start()) != 0) {
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fprintf(stderr,
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"expected: \n"
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"%s\n"
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"disassembled: \n"
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"%s\n\n",
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compare_string, disasm_buffer.start());
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return false;
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}
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return true;
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}
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// Setup V8 to a state where we can at least run the assembler and
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// disassembler. Declare the variables and allocate the data structures used
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// in the rest of the macros.
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#define SETUP() \
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InitializeVM(); \
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v8::HandleScope scope; \
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byte *buffer = reinterpret_cast<byte*>(malloc(4*1024)); \
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Assembler assm(buffer, 4*1024); \
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bool failure = false;
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// This macro assembles one instruction using the preallocated assembler and
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// disassembles the generated instruction, comparing the output to the expected
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// value. If the comparison fails an error message is printed, but the test
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// continues to run until the end.
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#define COMPARE(asm_, compare_string) \
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{ \
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int pc_offset = assm.pc_offset(); \
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byte *pc = &buffer[pc_offset]; \
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assm.asm_; \
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if (!DisassembleAndCompare(pc, compare_string)) failure = true; \
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}
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// Verify that all invocations of the COMPARE macro passed successfully.
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// Exit with a failure if at least one of the tests failed.
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#define VERIFY_RUN() \
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if (failure) { \
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V8_Fatal(__FILE__, __LINE__, "ARM Disassembler tests failed.\n"); \
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}
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TEST(Type0) {
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SETUP();
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COMPARE(and_(r0, r1, Operand(r2)),
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"e0010002 and r0, r1, r2");
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COMPARE(and_(r1, r2, Operand(r3), LeaveCC),
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"e0021003 and r1, r2, r3");
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COMPARE(and_(r2, r3, Operand(r4), SetCC),
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"e0132004 ands r2, r3, r4");
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COMPARE(and_(r3, r4, Operand(r5), LeaveCC, eq),
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"00043005 andeq r3, r4, r5");
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COMPARE(eor(r4, r5, Operand(r6, LSL, 0)),
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"e0254006 eor r4, r5, r6");
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COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
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"e0354087 eors r4, r5, r7, lsl #1");
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COMPARE(eor(r4, r5, Operand(r8, LSL, 2), LeaveCC, ne),
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"10254108 eorne r4, r5, r8, lsl #2");
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COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
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"20354189 eorcss r4, r5, r9, lsl #3");
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COMPARE(sub(r5, r6, Operand(r10, LSL, 31), LeaveCC, hs),
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"20465f8a subcs r5, r6, r10, lsl #31");
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COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
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"30565f0a subccs r5, r6, r10, lsl #30");
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COMPARE(sub(r5, r6, Operand(r10, LSL, 24), LeaveCC, lo),
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"30465c0a subcc r5, r6, r10, lsl #24");
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COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
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"4056580a submis r5, r6, r10, lsl #16");
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COMPARE(rsb(r6, r7, Operand(fp)),
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"e067600b rsb r6, r7, fp");
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COMPARE(rsb(r6, r7, Operand(fp, LSR, 1)),
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"e06760ab rsb r6, r7, fp, lsr #1");
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COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
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"e077602b rsbs r6, r7, fp, lsr #32");
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COMPARE(rsb(r6, r7, Operand(fp, LSR, 31), LeaveCC, pl),
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"50676fab rsbpl r6, r7, fp, lsr #31");
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COMPARE(add(r7, r8, Operand(ip, ASR, 1)),
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"e08870cc add r7, r8, ip, asr #1");
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COMPARE(add(r7, r8, Operand(ip, ASR, 0)),
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"e088704c add r7, r8, ip, asr #32");
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COMPARE(add(r7, r8, Operand(ip), SetCC),
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"e098700c adds r7, r8, ip");
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COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
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"60987fcc addvss r7, r8, ip, asr #31");
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COMPARE(adc(r7, fp, Operand(ip, ASR, 5)),
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"e0ab72cc adc r7, fp, ip, asr #5");
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COMPARE(adc(r4, ip, Operand(ip, ASR, 1), LeaveCC, vc),
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"70ac40cc adcvc r4, ip, ip, asr #1");
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COMPARE(adc(r5, sp, Operand(ip), SetCC),
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"e0bd500c adcs r5, sp, ip");
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COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc),
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"70be8fcc adcvcs r8, lr, ip, asr #31");
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COMPARE(sbc(r7, r1, Operand(ip, ROR, 1), LeaveCC, hi),
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"80c170ec sbchi r7, r1, ip, ror #1");
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COMPARE(sbc(r7, r9, Operand(ip, ROR, 4)),
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"e0c9726c sbc r7, r9, ip, ror #4");
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COMPARE(sbc(r7, r10, Operand(ip), SetCC),
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"e0da700c sbcs r7, r10, ip");
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COMPARE(sbc(r7, ip, Operand(ip, ROR, 31), SetCC, hi),
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"80dc7fec sbchis r7, ip, ip, ror #31");
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COMPARE(rsc(r7, r8, Operand(ip, LSL, r0)),
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"e0e8701c rsc r7, r8, ip, lsl r0");
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COMPARE(rsc(r7, r8, Operand(ip, LSL, r1)),
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"e0e8711c rsc r7, r8, ip, lsl r1");
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COMPARE(rsc(r7, r8, Operand(ip), SetCC),
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"e0f8700c rscs r7, r8, ip");
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COMPARE(rsc(r7, r8, Operand(ip, LSL, r3), SetCC, ls),
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"90f8731c rsclss r7, r8, ip, lsl r3");
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COMPARE(tst(r7, Operand(r5, ASR, ip), ge),
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"a1170c55 tstge r7, r5, asr ip");
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COMPARE(tst(r7, Operand(r6, ASR, sp)),
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"e1170d56 tst r7, r6, asr sp");
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COMPARE(tst(r7, Operand(r7), ge),
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"a1170007 tstge r7, r7");
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COMPARE(tst(r7, Operand(r8, ASR, fp), ge),
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"a1170b58 tstge r7, r8, asr fp");
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COMPARE(teq(r7, Operand(r5, ROR, r0), lt),
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"b1370075 teqlt r7, r5, ror r0");
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COMPARE(teq(r7, Operand(r6, ROR, lr)),
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"e1370e76 teq r7, r6, ror lr");
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COMPARE(teq(r7, Operand(r7), lt),
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"b1370007 teqlt r7, r7");
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COMPARE(teq(r7, Operand(r8, ROR, r1)),
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"e1370178 teq r7, r8, ror r1");
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COMPARE(cmp(r7, Operand(r4)),
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"e1570004 cmp r7, r4");
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COMPARE(cmp(r7, Operand(r6, LSL, 1), gt),
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"c1570086 cmpgt r7, r6, lsl #1");
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COMPARE(cmp(r7, Operand(r8, LSR, 3), gt),
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"c15701a8 cmpgt r7, r8, lsr #3");
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COMPARE(cmp(r7, Operand(r8, ASR, 19)),
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"e15709c8 cmp r7, r8, asr #19");
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COMPARE(cmn(r0, Operand(r4)),
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"e1700004 cmn r0, r4");
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COMPARE(cmn(r1, Operand(r6, ROR, 1)),
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"e17100e6 cmn r1, r6, ror #1");
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COMPARE(cmn(r2, Operand(r8)),
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"e1720008 cmn r2, r8");
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COMPARE(cmn(r3, Operand(fp), le),
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"d173000b cmnle r3, fp");
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COMPARE(orr(r7, r8, Operand(lr), LeaveCC, al),
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"e188700e orr r7, r8, lr");
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COMPARE(orr(r7, r8, Operand(fp)),
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"e188700b orr r7, r8, fp");
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COMPARE(orr(r7, r8, Operand(sp), SetCC),
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"e198700d orrs r7, r8, sp");
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COMPARE(orr(r7, r8, Operand(ip), SetCC, al),
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"e198700c orrs r7, r8, ip");
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COMPARE(mov(r0, Operand(r1), LeaveCC, eq),
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"01a00001 moveq r0, r1");
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COMPARE(mov(r0, Operand(r2)),
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"e1a00002 mov r0, r2");
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COMPARE(mov(r0, Operand(r3), SetCC),
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"e1b00003 movs r0, r3");
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COMPARE(mov(r0, Operand(r4), SetCC, pl),
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"51b00004 movpls r0, r4");
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COMPARE(bic(r0, lr, Operand(r1), LeaveCC, vs),
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"61ce0001 bicvs r0, lr, r1");
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COMPARE(bic(r0, r9, Operand(r2), LeaveCC, vc),
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"71c90002 bicvc r0, r9, r2");
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COMPARE(bic(r0, r5, Operand(r3), SetCC),
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"e1d50003 bics r0, r5, r3");
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COMPARE(bic(r0, r1, Operand(r4), SetCC, pl),
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"51d10004 bicpls r0, r1, r4");
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COMPARE(mvn(r10, Operand(r1)),
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"e1e0a001 mvn r10, r1");
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COMPARE(mvn(r9, Operand(r2)),
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"e1e09002 mvn r9, r2");
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COMPARE(mvn(r0, Operand(r3), SetCC),
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"e1f00003 mvns r0, r3");
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COMPARE(mvn(r5, Operand(r4), SetCC, cc),
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"31f05004 mvnccs r5, r4");
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// Instructions autotransformed by the assembler.
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// mov -> mvn.
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COMPARE(mov(r3, Operand(-1), LeaveCC, al),
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"e3e03000 mvn r3, #0");
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COMPARE(mov(r4, Operand(-2), SetCC, al),
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"e3f04001 mvns r4, #1");
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COMPARE(mov(r5, Operand(0x0ffffff0), SetCC, ne),
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"13f052ff mvnnes r5, #-268435441");
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COMPARE(mov(r6, Operand(-1), LeaveCC, ne),
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"13e06000 mvnne r6, #0");
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// mvn -> mov.
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COMPARE(mvn(r3, Operand(-1), LeaveCC, al),
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"e3a03000 mov r3, #0");
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COMPARE(mvn(r4, Operand(-2), SetCC, al),
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"e3b04001 movs r4, #1");
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COMPARE(mvn(r5, Operand(0x0ffffff0), SetCC, ne),
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"13b052ff movnes r5, #-268435441");
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COMPARE(mvn(r6, Operand(-1), LeaveCC, ne),
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"13a06000 movne r6, #0");
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// mov -> movw.
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if (CpuFeatures::IsSupported(ARMv7)) {
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COMPARE(mov(r5, Operand(0x01234), LeaveCC, ne),
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"13015234 movwne r5, #4660");
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// We only disassemble one instruction so the eor instruction is not here.
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COMPARE(eor(r5, r4, Operand(0x1234), LeaveCC, ne),
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"1301c234 movwne ip, #4660");
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// Movw can't do setcc so we don't get that here. Mov immediate with setcc
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// is pretty strange anyway.
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COMPARE(mov(r5, Operand(0x01234), SetCC, ne),
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"159fc000 ldrne ip, [pc, #+0]");
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// We only disassemble one instruction so the eor instruction is not here.
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// The eor does the setcc so we get a movw here.
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COMPARE(eor(r5, r4, Operand(0x1234), SetCC, ne),
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"1301c234 movwne ip, #4660");
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COMPARE(movt(r5, 0x4321, ne),
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"13445321 movtne r5, #17185");
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COMPARE(movw(r5, 0xabcd, eq),
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"030a5bcd movweq r5, #43981");
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}
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// Eor doesn't have an eor-negative variant, but we can do an mvn followed by
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// an eor to get the same effect.
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COMPARE(eor(r5, r4, Operand(0xffffff34), SetCC, ne),
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"13e0c0cb mvnne ip, #203");
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// and <-> bic.
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COMPARE(and_(r3, r5, Operand(0xfc03ffff)),
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"e3c537ff bic r3, r5, #66846720");
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COMPARE(bic(r3, r5, Operand(0xfc03ffff)),
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"e20537ff and r3, r5, #66846720");
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// sub <-> add.
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COMPARE(add(r3, r5, Operand(-1024)),
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"e2453b01 sub r3, r5, #1024");
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COMPARE(sub(r3, r5, Operand(-1024)),
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"e2853b01 add r3, r5, #1024");
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// cmp <-> cmn.
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COMPARE(cmp(r3, Operand(-1024)),
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"e3730b01 cmn r3, #1024");
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COMPARE(cmn(r3, Operand(-1024)),
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"e3530b01 cmp r3, #1024");
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// Miscellaneous instructions encoded as type 0.
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COMPARE(blx(ip),
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"e12fff3c blx ip");
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COMPARE(bkpt(0),
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"e1200070 bkpt 0");
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COMPARE(bkpt(0xffff),
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"e12fff7f bkpt 65535");
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COMPARE(clz(r6, r7),
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"e16f6f17 clz r6, r7");
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VERIFY_RUN();
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}
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TEST(Type1) {
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SETUP();
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COMPARE(and_(r0, r1, Operand(0x00000000)),
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"e2010000 and r0, r1, #0");
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COMPARE(and_(r1, r2, Operand(0x00000001), LeaveCC),
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"e2021001 and r1, r2, #1");
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COMPARE(and_(r2, r3, Operand(0x00000010), SetCC),
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"e2132010 ands r2, r3, #16");
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COMPARE(and_(r3, r4, Operand(0x00000100), LeaveCC, eq),
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"02043c01 andeq r3, r4, #256");
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COMPARE(and_(r4, r5, Operand(0x00001000), SetCC, ne),
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"12154a01 andnes r4, r5, #4096");
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COMPARE(eor(r4, r5, Operand(0x00001000)),
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"e2254a01 eor r4, r5, #4096");
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COMPARE(eor(r4, r4, Operand(0x00010000), LeaveCC),
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"e2244801 eor r4, r4, #65536");
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COMPARE(eor(r4, r3, Operand(0x00100000), SetCC),
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"e2334601 eors r4, r3, #1048576");
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COMPARE(eor(r4, r2, Operand(0x01000000), LeaveCC, cs),
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"22224401 eorcs r4, r2, #16777216");
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COMPARE(eor(r4, r1, Operand(0x10000000), SetCC, cc),
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"32314201 eorccs r4, r1, #268435456");
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VERIFY_RUN();
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}
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TEST(Type3) {
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SETUP();
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if (CpuFeatures::IsSupported(ARMv7)) {
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COMPARE(ubfx(r0, r1, 5, 10),
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"e7e902d1 ubfx r0, r1, #5, #10");
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COMPARE(ubfx(r1, r0, 5, 10),
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"e7e912d0 ubfx r1, r0, #5, #10");
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COMPARE(ubfx(r0, r1, 31, 1),
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"e7e00fd1 ubfx r0, r1, #31, #1");
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COMPARE(ubfx(r1, r0, 31, 1),
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"e7e01fd0 ubfx r1, r0, #31, #1");
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COMPARE(sbfx(r0, r1, 5, 10),
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"e7a902d1 sbfx r0, r1, #5, #10");
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COMPARE(sbfx(r1, r0, 5, 10),
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"e7a912d0 sbfx r1, r0, #5, #10");
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COMPARE(sbfx(r0, r1, 31, 1),
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"e7a00fd1 sbfx r0, r1, #31, #1");
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COMPARE(sbfx(r1, r0, 31, 1),
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"e7a01fd0 sbfx r1, r0, #31, #1");
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COMPARE(bfc(r0, 5, 10),
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"e7ce029f bfc r0, #5, #10");
|
|
COMPARE(bfc(r1, 5, 10),
|
|
"e7ce129f bfc r1, #5, #10");
|
|
COMPARE(bfc(r0, 31, 1),
|
|
"e7df0f9f bfc r0, #31, #1");
|
|
COMPARE(bfc(r1, 31, 1),
|
|
"e7df1f9f bfc r1, #31, #1");
|
|
|
|
COMPARE(bfi(r0, r1, 5, 10),
|
|
"e7ce0291 bfi r0, r1, #5, #10");
|
|
COMPARE(bfi(r1, r0, 5, 10),
|
|
"e7ce1290 bfi r1, r0, #5, #10");
|
|
COMPARE(bfi(r0, r1, 31, 1),
|
|
"e7df0f91 bfi r0, r1, #31, #1");
|
|
COMPARE(bfi(r1, r0, 31, 1),
|
|
"e7df1f90 bfi r1, r0, #31, #1");
|
|
}
|
|
|
|
VERIFY_RUN();
|
|
}
|
|
|