zhengxing.li 3145befb3d [turbofan][X64] Movzxbl/Movsxbl/Movzxwl/Movsxwl also zero extend to 64bit. ... movzxbl/movsxbl/movzxwl/movsxwl operations implicitly zero-extend to 64-bit on x64, So It's not necessary to generate a "movl" instruction to zero-extend. For example, movzxbl/movl instruction sequence occurs frequently in v8 interpreter bytecode handler. such as: kind = BYTECODE_HANDLER name = LdaSmi compiler = turbofan Instructions (size = 76) 0x184870a3ce40 0 430fbe442601 movsxbl rax,[r14+r12*1+0x1] 0x184870a3ce46 6 48c1e020 REX.W shlq rax, 32 0x184870a3ce4a 10 498d5c2402 REX.W leaq rbx,[r12+0x2] 0x184870a3ce4f 15 420fb61433 movzxbl rdx,[rbx+r14*1] 0x184870a3ce54 20 8bd2 movl rdx,rdx <---------------------- here is a redundant "movl" 0x184870a3ce56 22 4883fa1e REX.W cmpq rdx,0x1e 0x184870a3ce5a 26 0f8518000000 jnz 56 (0x184870a3ce78) This CL also referenced to CL #36038 (https://codereview.chromium.org/1950013003 ) for adding test cases. BUG= Review-Url: https://codereview.chromium.org/2427483002 Cr-Commit-Position: refs/heads/master@{#40375}		2016-10-18 03:40:37 +00:00
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instruction-selector-x64-unittest.cc	[turbofan][X64] Movzxbl/Movsxbl/Movzxwl/Movsxwl also zero extend to 64bit.	2016-10-18 03:40:37 +00:00