ac320205b9
emitted as part of the safepoint tables. Always emit the constant pool as part of generating deferred code (whether or not there actually is any deferred code) and ASSERT that there is no pending relocation info while using db and dd to write tables. Review URL: http://codereview.chromium.org/6360003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6347 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
1432 lines
47 KiB
C++
1432 lines
47 KiB
C++
// Copyright (c) 1994-2006 Sun Microsystems Inc.
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// All Rights Reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// - Redistribution in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// - Neither the name of Sun Microsystems or the names of contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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// OF THE POSSIBILITY OF SUCH DAMAGE.
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// The original source code covered by the above license above has been
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// modified significantly by Google Inc.
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// Copyright 2010 the V8 project authors. All rights reserved.
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// A light-weight ARM Assembler
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// Generates user mode instructions for the ARM architecture up to version 5
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#ifndef V8_ARM_ASSEMBLER_ARM_H_
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#define V8_ARM_ASSEMBLER_ARM_H_
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#include <stdio.h>
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#include "assembler.h"
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#include "serialize.h"
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namespace v8 {
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namespace internal {
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// CPU Registers.
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//
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// 1) We would prefer to use an enum, but enum values are assignment-
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// compatible with int, which has caused code-generation bugs.
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//
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// 2) We would prefer to use a class instead of a struct but we don't like
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// the register initialization to depend on the particular initialization
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// order (which appears to be different on OS X, Linux, and Windows for the
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// installed versions of C++ we tried). Using a struct permits C-style
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// "initialization". Also, the Register objects cannot be const as this
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// forces initialization stubs in MSVC, making us dependent on initialization
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// order.
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//
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// 3) By not using an enum, we are possibly preventing the compiler from
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// doing certain constant folds, which may significantly reduce the
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// code generated for some assembly instructions (because they boil down
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// to a few constants). If this is a problem, we could change the code
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// such that we use an enum in optimized mode, and the struct in debug
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// mode. This way we get the compile-time error checking in debug mode
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// and best performance in optimized code.
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// Core register
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struct Register {
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static const int kNumRegisters = 16;
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static const int kNumAllocatableRegisters = 8;
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static int ToAllocationIndex(Register reg) {
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ASSERT(reg.code() < kNumAllocatableRegisters);
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return reg.code();
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}
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static Register FromAllocationIndex(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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return from_code(index);
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}
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static const char* AllocationIndexToString(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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const char* const names[] = {
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"r0",
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"r1",
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"r2",
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"r3",
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"r4",
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"r5",
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"r6",
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"r7",
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};
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return names[index];
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}
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static Register from_code(int code) {
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Register r = { code };
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return r;
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}
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bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
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bool is(Register reg) const { return code_ == reg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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void set_code(int code) {
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code_ = code;
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ASSERT(is_valid());
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}
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// Unfortunately we can't make this private in a struct.
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int code_;
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};
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const Register no_reg = { -1 };
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const Register r0 = { 0 };
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const Register r1 = { 1 };
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const Register r2 = { 2 };
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const Register r3 = { 3 };
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const Register r4 = { 4 };
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const Register r5 = { 5 };
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const Register r6 = { 6 };
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const Register r7 = { 7 };
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const Register r8 = { 8 }; // Used as context register.
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const Register r9 = { 9 }; // Used as lithium codegen scratch register.
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const Register r10 = { 10 }; // Used as roots register.
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const Register fp = { 11 };
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const Register ip = { 12 };
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const Register sp = { 13 };
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const Register lr = { 14 };
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const Register pc = { 15 };
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// Single word VFP register.
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struct SwVfpRegister {
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bool is_valid() const { return 0 <= code_ && code_ < 32; }
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bool is(SwVfpRegister reg) const { return code_ == reg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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void split_code(int* vm, int* m) const {
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ASSERT(is_valid());
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*m = code_ & 0x1;
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*vm = code_ >> 1;
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}
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int code_;
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};
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// Double word VFP register.
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struct DwVfpRegister {
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// d0 has been excluded from allocation. This is following ia32
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// where xmm0 is excluded. This should be revisited.
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// Currently d0 is used as a scratch register.
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// d1 has also been excluded from allocation to be used as a scratch
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// register as well.
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static const int kNumRegisters = 16;
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static const int kNumAllocatableRegisters = 15;
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static int ToAllocationIndex(DwVfpRegister reg) {
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ASSERT(reg.code() != 0);
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return reg.code() - 1;
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}
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static DwVfpRegister FromAllocationIndex(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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return from_code(index + 1);
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}
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static const char* AllocationIndexToString(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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const char* const names[] = {
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"d1",
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"d2",
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"d3",
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"d4",
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"d5",
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"d6",
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"d7",
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"d8",
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"d9",
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"d10",
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"d11",
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"d12",
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"d13",
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"d14",
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"d15"
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};
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return names[index];
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}
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static DwVfpRegister from_code(int code) {
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DwVfpRegister r = { code };
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return r;
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}
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// Supporting d0 to d15, can be later extended to d31.
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bool is_valid() const { return 0 <= code_ && code_ < 16; }
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bool is(DwVfpRegister reg) const { return code_ == reg.code_; }
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SwVfpRegister low() const {
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SwVfpRegister reg;
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reg.code_ = code_ * 2;
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ASSERT(reg.is_valid());
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return reg;
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}
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SwVfpRegister high() const {
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SwVfpRegister reg;
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reg.code_ = (code_ * 2) + 1;
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ASSERT(reg.is_valid());
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return reg;
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}
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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void split_code(int* vm, int* m) const {
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ASSERT(is_valid());
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*m = (code_ & 0x10) >> 4;
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*vm = code_ & 0x0F;
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}
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int code_;
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};
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typedef DwVfpRegister DoubleRegister;
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// Support for the VFP registers s0 to s31 (d0 to d15).
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// Note that "s(N):s(N+1)" is the same as "d(N/2)".
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const SwVfpRegister s0 = { 0 };
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const SwVfpRegister s1 = { 1 };
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const SwVfpRegister s2 = { 2 };
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const SwVfpRegister s3 = { 3 };
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const SwVfpRegister s4 = { 4 };
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const SwVfpRegister s5 = { 5 };
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const SwVfpRegister s6 = { 6 };
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const SwVfpRegister s7 = { 7 };
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const SwVfpRegister s8 = { 8 };
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const SwVfpRegister s9 = { 9 };
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const SwVfpRegister s10 = { 10 };
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const SwVfpRegister s11 = { 11 };
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const SwVfpRegister s12 = { 12 };
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const SwVfpRegister s13 = { 13 };
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const SwVfpRegister s14 = { 14 };
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const SwVfpRegister s15 = { 15 };
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const SwVfpRegister s16 = { 16 };
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const SwVfpRegister s17 = { 17 };
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const SwVfpRegister s18 = { 18 };
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const SwVfpRegister s19 = { 19 };
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const SwVfpRegister s20 = { 20 };
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const SwVfpRegister s21 = { 21 };
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const SwVfpRegister s22 = { 22 };
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const SwVfpRegister s23 = { 23 };
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const SwVfpRegister s24 = { 24 };
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const SwVfpRegister s25 = { 25 };
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const SwVfpRegister s26 = { 26 };
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const SwVfpRegister s27 = { 27 };
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const SwVfpRegister s28 = { 28 };
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const SwVfpRegister s29 = { 29 };
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const SwVfpRegister s30 = { 30 };
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const SwVfpRegister s31 = { 31 };
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const DwVfpRegister d0 = { 0 };
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const DwVfpRegister d1 = { 1 };
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const DwVfpRegister d2 = { 2 };
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const DwVfpRegister d3 = { 3 };
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const DwVfpRegister d4 = { 4 };
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const DwVfpRegister d5 = { 5 };
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const DwVfpRegister d6 = { 6 };
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const DwVfpRegister d7 = { 7 };
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const DwVfpRegister d8 = { 8 };
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const DwVfpRegister d9 = { 9 };
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const DwVfpRegister d10 = { 10 };
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const DwVfpRegister d11 = { 11 };
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const DwVfpRegister d12 = { 12 };
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const DwVfpRegister d13 = { 13 };
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const DwVfpRegister d14 = { 14 };
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const DwVfpRegister d15 = { 15 };
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// VFP FPSCR constants.
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static const uint32_t kVFPNConditionFlagBit = 1 << 31;
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static const uint32_t kVFPZConditionFlagBit = 1 << 30;
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static const uint32_t kVFPCConditionFlagBit = 1 << 29;
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static const uint32_t kVFPVConditionFlagBit = 1 << 28;
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static const uint32_t kVFPFlushToZeroMask = 1 << 24;
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static const uint32_t kVFPRoundingModeMask = 3 << 22;
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static const uint32_t kVFPRoundToMinusInfinityBits = 2 << 22;
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static const uint32_t kVFPExceptionMask = 0xf;
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// Coprocessor register
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struct CRegister {
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bool is_valid() const { return 0 <= code_ && code_ < 16; }
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bool is(CRegister creg) const { return code_ == creg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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// Unfortunately we can't make this private in a struct.
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int code_;
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};
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const CRegister no_creg = { -1 };
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const CRegister cr0 = { 0 };
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const CRegister cr1 = { 1 };
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const CRegister cr2 = { 2 };
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const CRegister cr3 = { 3 };
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const CRegister cr4 = { 4 };
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const CRegister cr5 = { 5 };
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const CRegister cr6 = { 6 };
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const CRegister cr7 = { 7 };
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const CRegister cr8 = { 8 };
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const CRegister cr9 = { 9 };
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const CRegister cr10 = { 10 };
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const CRegister cr11 = { 11 };
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const CRegister cr12 = { 12 };
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const CRegister cr13 = { 13 };
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const CRegister cr14 = { 14 };
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const CRegister cr15 = { 15 };
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// Coprocessor number
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enum Coprocessor {
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p0 = 0,
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p1 = 1,
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p2 = 2,
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p3 = 3,
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p4 = 4,
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p5 = 5,
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p6 = 6,
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p7 = 7,
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p8 = 8,
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p9 = 9,
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p10 = 10,
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p11 = 11,
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p12 = 12,
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p13 = 13,
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p14 = 14,
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p15 = 15
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};
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// Condition field in instructions.
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enum Condition {
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// any value < 0 is considered no_condition
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no_condition = -1,
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eq = 0 << 28, // Z set equal.
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ne = 1 << 28, // Z clear not equal.
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nz = 1 << 28, // Z clear not zero.
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cs = 2 << 28, // C set carry set.
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hs = 2 << 28, // C set unsigned higher or same.
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cc = 3 << 28, // C clear carry clear.
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lo = 3 << 28, // C clear unsigned lower.
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mi = 4 << 28, // N set negative.
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pl = 5 << 28, // N clear positive or zero.
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vs = 6 << 28, // V set overflow.
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vc = 7 << 28, // V clear no overflow.
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hi = 8 << 28, // C set, Z clear unsigned higher.
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ls = 9 << 28, // C clear or Z set unsigned lower or same.
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ge = 10 << 28, // N == V greater or equal.
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lt = 11 << 28, // N != V less than.
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gt = 12 << 28, // Z clear, N == V greater than.
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le = 13 << 28, // Z set or N != V less then or equal
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al = 14 << 28 // always.
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};
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// Returns the equivalent of !cc.
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inline Condition NegateCondition(Condition cc) {
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ASSERT(cc != al);
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return static_cast<Condition>(cc ^ ne);
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}
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// Corresponds to transposing the operands of a comparison.
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inline Condition ReverseCondition(Condition cc) {
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switch (cc) {
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case lo:
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return hi;
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case hi:
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return lo;
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case hs:
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return ls;
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case ls:
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return hs;
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case lt:
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return gt;
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case gt:
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return lt;
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case ge:
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return le;
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case le:
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return ge;
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default:
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return cc;
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};
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}
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// Branch hints are not used on the ARM. They are defined so that they can
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// appear in shared function signatures, but will be ignored in ARM
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// implementations.
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enum Hint { no_hint };
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// Hints are not used on the arm. Negating is trivial.
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inline Hint NegateHint(Hint ignored) { return no_hint; }
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// -----------------------------------------------------------------------------
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// Addressing modes and instruction variants
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// Shifter operand shift operation
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enum ShiftOp {
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LSL = 0 << 5,
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LSR = 1 << 5,
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ASR = 2 << 5,
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ROR = 3 << 5,
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RRX = -1
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};
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// Condition code updating mode
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enum SBit {
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SetCC = 1 << 20, // set condition code
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LeaveCC = 0 << 20 // leave condition code unchanged
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};
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// Status register selection
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enum SRegister {
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CPSR = 0 << 22,
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SPSR = 1 << 22
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};
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// Status register fields
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enum SRegisterField {
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CPSR_c = CPSR | 1 << 16,
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CPSR_x = CPSR | 1 << 17,
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CPSR_s = CPSR | 1 << 18,
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CPSR_f = CPSR | 1 << 19,
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SPSR_c = SPSR | 1 << 16,
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SPSR_x = SPSR | 1 << 17,
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SPSR_s = SPSR | 1 << 18,
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SPSR_f = SPSR | 1 << 19
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};
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// Status register field mask (or'ed SRegisterField enum values)
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typedef uint32_t SRegisterFieldMask;
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// Memory operand addressing mode
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enum AddrMode {
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// bit encoding P U W
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Offset = (8|4|0) << 21, // offset (without writeback to base)
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PreIndex = (8|4|1) << 21, // pre-indexed addressing with writeback
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PostIndex = (0|4|0) << 21, // post-indexed addressing with writeback
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NegOffset = (8|0|0) << 21, // negative offset (without writeback to base)
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NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback
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NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback
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};
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// Load/store multiple addressing mode
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enum BlockAddrMode {
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// bit encoding P U W
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da = (0|0|0) << 21, // decrement after
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ia = (0|4|0) << 21, // increment after
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db = (8|0|0) << 21, // decrement before
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ib = (8|4|0) << 21, // increment before
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da_w = (0|0|1) << 21, // decrement after with writeback to base
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ia_w = (0|4|1) << 21, // increment after with writeback to base
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db_w = (8|0|1) << 21, // decrement before with writeback to base
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ib_w = (8|4|1) << 21 // increment before with writeback to base
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};
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// Coprocessor load/store operand size
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enum LFlag {
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Long = 1 << 22, // long load/store coprocessor
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Short = 0 << 22 // short load/store coprocessor
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};
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// -----------------------------------------------------------------------------
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// Machine instruction Operands
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// Class Operand represents a shifter operand in data processing instructions
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class Operand BASE_EMBEDDED {
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public:
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// immediate
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INLINE(explicit Operand(int32_t immediate,
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|
RelocInfo::Mode rmode = RelocInfo::NONE));
|
|
INLINE(explicit Operand(const ExternalReference& f));
|
|
INLINE(explicit Operand(const char* s));
|
|
explicit Operand(Handle<Object> handle);
|
|
INLINE(explicit Operand(Smi* value));
|
|
|
|
// rm
|
|
INLINE(explicit Operand(Register rm));
|
|
|
|
// rm <shift_op> shift_imm
|
|
explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
|
|
|
|
// rm <shift_op> rs
|
|
explicit Operand(Register rm, ShiftOp shift_op, Register rs);
|
|
|
|
// Return true if this is a register operand.
|
|
INLINE(bool is_reg() const);
|
|
|
|
// Return true of this operand fits in one instruction so that no
|
|
// 2-instruction solution with a load into the ip register is necessary.
|
|
bool is_single_instruction() const;
|
|
bool must_use_constant_pool() const;
|
|
|
|
inline int32_t immediate() const {
|
|
ASSERT(!rm_.is_valid());
|
|
return imm32_;
|
|
}
|
|
|
|
Register rm() const { return rm_; }
|
|
Register rs() const { return rs_; }
|
|
ShiftOp shift_op() const { return shift_op_; }
|
|
|
|
private:
|
|
Register rm_;
|
|
Register rs_;
|
|
ShiftOp shift_op_;
|
|
int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg
|
|
int32_t imm32_; // valid if rm_ == no_reg
|
|
RelocInfo::Mode rmode_;
|
|
|
|
friend class Assembler;
|
|
};
|
|
|
|
|
|
// Class MemOperand represents a memory operand in load and store instructions
|
|
class MemOperand BASE_EMBEDDED {
|
|
public:
|
|
// [rn +/- offset] Offset/NegOffset
|
|
// [rn +/- offset]! PreIndex/NegPreIndex
|
|
// [rn], +/- offset PostIndex/NegPostIndex
|
|
// offset is any signed 32-bit value; offset is first loaded to register ip if
|
|
// it does not fit the addressing mode (12-bit unsigned and sign bit)
|
|
explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset);
|
|
|
|
// [rn +/- rm] Offset/NegOffset
|
|
// [rn +/- rm]! PreIndex/NegPreIndex
|
|
// [rn], +/- rm PostIndex/NegPostIndex
|
|
explicit MemOperand(Register rn, Register rm, AddrMode am = Offset);
|
|
|
|
// [rn +/- rm <shift_op> shift_imm] Offset/NegOffset
|
|
// [rn +/- rm <shift_op> shift_imm]! PreIndex/NegPreIndex
|
|
// [rn], +/- rm <shift_op> shift_imm PostIndex/NegPostIndex
|
|
explicit MemOperand(Register rn, Register rm,
|
|
ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
|
|
|
|
void set_offset(int32_t offset) {
|
|
ASSERT(rm_.is(no_reg));
|
|
offset_ = offset;
|
|
}
|
|
|
|
uint32_t offset() {
|
|
ASSERT(rm_.is(no_reg));
|
|
return offset_;
|
|
}
|
|
|
|
Register rn() const { return rn_; }
|
|
Register rm() const { return rm_; }
|
|
|
|
private:
|
|
Register rn_; // base
|
|
Register rm_; // register offset
|
|
int32_t offset_; // valid if rm_ == no_reg
|
|
ShiftOp shift_op_;
|
|
int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg
|
|
AddrMode am_; // bits P, U, and W
|
|
|
|
friend class Assembler;
|
|
};
|
|
|
|
// CpuFeatures keeps track of which features are supported by the target CPU.
|
|
// Supported features must be enabled by a Scope before use.
|
|
class CpuFeatures : public AllStatic {
|
|
public:
|
|
// Detect features of the target CPU. Set safe defaults if the serializer
|
|
// is enabled (snapshots must be portable).
|
|
static void Probe(bool portable);
|
|
|
|
// Check whether a feature is supported by the target CPU.
|
|
static bool IsSupported(CpuFeature f) {
|
|
if (f == VFP3 && !FLAG_enable_vfp3) return false;
|
|
return (supported_ & (1u << f)) != 0;
|
|
}
|
|
|
|
// Check whether a feature is currently enabled.
|
|
static bool IsEnabled(CpuFeature f) {
|
|
return (enabled_ & (1u << f)) != 0;
|
|
}
|
|
|
|
// Enable a specified feature within a scope.
|
|
class Scope BASE_EMBEDDED {
|
|
#ifdef DEBUG
|
|
public:
|
|
explicit Scope(CpuFeature f) {
|
|
ASSERT(CpuFeatures::IsSupported(f));
|
|
ASSERT(!Serializer::enabled() ||
|
|
(found_by_runtime_probing_ & (1u << f)) == 0);
|
|
old_enabled_ = CpuFeatures::enabled_;
|
|
CpuFeatures::enabled_ |= 1u << f;
|
|
}
|
|
~Scope() { CpuFeatures::enabled_ = old_enabled_; }
|
|
private:
|
|
unsigned old_enabled_;
|
|
#else
|
|
public:
|
|
explicit Scope(CpuFeature f) {}
|
|
#endif
|
|
};
|
|
|
|
private:
|
|
static unsigned supported_;
|
|
static unsigned enabled_;
|
|
static unsigned found_by_runtime_probing_;
|
|
};
|
|
|
|
|
|
typedef int32_t Instr;
|
|
|
|
|
|
extern const Instr kMovLrPc;
|
|
extern const Instr kLdrPCMask;
|
|
extern const Instr kLdrPCPattern;
|
|
extern const Instr kBlxRegMask;
|
|
extern const Instr kBlxRegPattern;
|
|
|
|
extern const Instr kMovMvnMask;
|
|
extern const Instr kMovMvnPattern;
|
|
extern const Instr kMovMvnFlip;
|
|
|
|
extern const Instr kMovLeaveCCMask;
|
|
extern const Instr kMovLeaveCCPattern;
|
|
extern const Instr kMovwMask;
|
|
extern const Instr kMovwPattern;
|
|
extern const Instr kMovwLeaveCCFlip;
|
|
|
|
extern const Instr kCmpCmnMask;
|
|
extern const Instr kCmpCmnPattern;
|
|
extern const Instr kCmpCmnFlip;
|
|
|
|
extern const Instr kALUMask;
|
|
extern const Instr kAddPattern;
|
|
extern const Instr kSubPattern;
|
|
extern const Instr kAndPattern;
|
|
extern const Instr kBicPattern;
|
|
extern const Instr kAddSubFlip;
|
|
extern const Instr kAndBicFlip;
|
|
|
|
class Assembler : public Malloced {
|
|
public:
|
|
// Create an assembler. Instructions and relocation information are emitted
|
|
// into a buffer, with the instructions starting from the beginning and the
|
|
// relocation information starting from the end of the buffer. See CodeDesc
|
|
// for a detailed comment on the layout (globals.h).
|
|
//
|
|
// If the provided buffer is NULL, the assembler allocates and grows its own
|
|
// buffer, and buffer_size determines the initial buffer size. The buffer is
|
|
// owned by the assembler and deallocated upon destruction of the assembler.
|
|
//
|
|
// If the provided buffer is not NULL, the assembler uses the provided buffer
|
|
// for code generation and assumes its size to be buffer_size. If the buffer
|
|
// is too small, a fatal error occurs. No deallocation of the buffer is done
|
|
// upon destruction of the assembler.
|
|
Assembler(void* buffer, int buffer_size);
|
|
~Assembler();
|
|
|
|
// GetCode emits any pending (non-emitted) code and fills the descriptor
|
|
// desc. GetCode() is idempotent; it returns the same result if no other
|
|
// Assembler functions are invoked in between GetCode() calls.
|
|
void GetCode(CodeDesc* desc);
|
|
|
|
// Label operations & relative jumps (PPUM Appendix D)
|
|
//
|
|
// Takes a branch opcode (cc) and a label (L) and generates
|
|
// either a backward branch or a forward branch and links it
|
|
// to the label fixup chain. Usage:
|
|
//
|
|
// Label L; // unbound label
|
|
// j(cc, &L); // forward branch to unbound label
|
|
// bind(&L); // bind label to the current pc
|
|
// j(cc, &L); // backward branch to bound label
|
|
// bind(&L); // illegal: a label may be bound only once
|
|
//
|
|
// Note: The same Label can be used for forward and backward branches
|
|
// but it may be bound only once.
|
|
|
|
void bind(Label* L); // binds an unbound label L to the current code position
|
|
|
|
// Returns the branch offset to the given label from the current code position
|
|
// Links the label to the current position if it is still unbound
|
|
// Manages the jump elimination optimization if the second parameter is true.
|
|
int branch_offset(Label* L, bool jump_elimination_allowed);
|
|
|
|
// Puts a labels target address at the given position.
|
|
// The high 8 bits are set to zero.
|
|
void label_at_put(Label* L, int at_offset);
|
|
|
|
// Return the address in the constant pool of the code target address used by
|
|
// the branch/call instruction at pc.
|
|
INLINE(static Address target_address_address_at(Address pc));
|
|
|
|
// Read/Modify the code target address in the branch/call instruction at pc.
|
|
INLINE(static Address target_address_at(Address pc));
|
|
INLINE(static void set_target_address_at(Address pc, Address target));
|
|
|
|
// This sets the branch destination (which is in the constant pool on ARM).
|
|
// This is for calls and branches within generated code.
|
|
inline static void set_target_at(Address constant_pool_entry, Address target);
|
|
|
|
// This sets the branch destination (which is in the constant pool on ARM).
|
|
// This is for calls and branches to runtime code.
|
|
inline static void set_external_target_at(Address constant_pool_entry,
|
|
Address target) {
|
|
set_target_at(constant_pool_entry, target);
|
|
}
|
|
|
|
// Here we are patching the address in the constant pool, not the actual call
|
|
// instruction. The address in the constant pool is the same size as a
|
|
// pointer.
|
|
static const int kCallTargetSize = kPointerSize;
|
|
static const int kExternalTargetSize = kPointerSize;
|
|
|
|
// Size of an instruction.
|
|
static const int kInstrSize = sizeof(Instr);
|
|
|
|
// Distance between the instruction referring to the address of the call
|
|
// target and the return address.
|
|
#ifdef USE_BLX
|
|
// Call sequence is:
|
|
// ldr ip, [pc, #...] @ call address
|
|
// blx ip
|
|
// @ return address
|
|
static const int kCallTargetAddressOffset = 2 * kInstrSize;
|
|
#else
|
|
// Call sequence is:
|
|
// mov lr, pc
|
|
// ldr pc, [pc, #...] @ call address
|
|
// @ return address
|
|
static const int kCallTargetAddressOffset = kInstrSize;
|
|
#endif
|
|
|
|
// Distance between start of patched return sequence and the emitted address
|
|
// to jump to.
|
|
#ifdef USE_BLX
|
|
// Patched return sequence is:
|
|
// ldr ip, [pc, #0] @ emited address and start
|
|
// blx ip
|
|
static const int kPatchReturnSequenceAddressOffset = 0 * kInstrSize;
|
|
#else
|
|
// Patched return sequence is:
|
|
// mov lr, pc @ start of sequence
|
|
// ldr pc, [pc, #-4] @ emited address
|
|
static const int kPatchReturnSequenceAddressOffset = kInstrSize;
|
|
#endif
|
|
|
|
// Distance between start of patched debug break slot and the emitted address
|
|
// to jump to.
|
|
#ifdef USE_BLX
|
|
// Patched debug break slot code is:
|
|
// ldr ip, [pc, #0] @ emited address and start
|
|
// blx ip
|
|
static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
|
|
#else
|
|
// Patched debug break slot code is:
|
|
// mov lr, pc @ start of sequence
|
|
// ldr pc, [pc, #-4] @ emited address
|
|
static const int kPatchDebugBreakSlotAddressOffset = kInstrSize;
|
|
#endif
|
|
|
|
// Difference between address of current opcode and value read from pc
|
|
// register.
|
|
static const int kPcLoadDelta = 8;
|
|
|
|
static const int kJSReturnSequenceInstructions = 4;
|
|
static const int kDebugBreakSlotInstructions = 3;
|
|
static const int kDebugBreakSlotLength =
|
|
kDebugBreakSlotInstructions * kInstrSize;
|
|
|
|
// ---------------------------------------------------------------------------
|
|
// Code generation
|
|
|
|
// Insert the smallest number of nop instructions
|
|
// possible to align the pc offset to a multiple
|
|
// of m. m must be a power of 2 (>= 4).
|
|
void Align(int m);
|
|
// Aligns code to something that's optimal for a jump target for the platform.
|
|
void CodeTargetAlign();
|
|
|
|
// Branch instructions
|
|
void b(int branch_offset, Condition cond = al);
|
|
void bl(int branch_offset, Condition cond = al);
|
|
void blx(int branch_offset); // v5 and above
|
|
void blx(Register target, Condition cond = al); // v5 and above
|
|
void bx(Register target, Condition cond = al); // v5 and above, plus v4t
|
|
|
|
// Convenience branch instructions using labels
|
|
void b(Label* L, Condition cond = al) {
|
|
b(branch_offset(L, cond == al), cond);
|
|
}
|
|
void b(Condition cond, Label* L) { b(branch_offset(L, cond == al), cond); }
|
|
void bl(Label* L, Condition cond = al) { bl(branch_offset(L, false), cond); }
|
|
void bl(Condition cond, Label* L) { bl(branch_offset(L, false), cond); }
|
|
void blx(Label* L) { blx(branch_offset(L, false)); } // v5 and above
|
|
|
|
// Data-processing instructions
|
|
|
|
void and_(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void eor(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void sub(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
void sub(Register dst, Register src1, Register src2,
|
|
SBit s = LeaveCC, Condition cond = al) {
|
|
sub(dst, src1, Operand(src2), s, cond);
|
|
}
|
|
|
|
void rsb(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void add(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
void add(Register dst, Register src1, Register src2,
|
|
SBit s = LeaveCC, Condition cond = al) {
|
|
add(dst, src1, Operand(src2), s, cond);
|
|
}
|
|
|
|
void adc(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void sbc(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void rsc(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void tst(Register src1, const Operand& src2, Condition cond = al);
|
|
void tst(Register src1, Register src2, Condition cond = al) {
|
|
tst(src1, Operand(src2), cond);
|
|
}
|
|
|
|
void teq(Register src1, const Operand& src2, Condition cond = al);
|
|
|
|
void cmp(Register src1, const Operand& src2, Condition cond = al);
|
|
void cmp(Register src1, Register src2, Condition cond = al) {
|
|
cmp(src1, Operand(src2), cond);
|
|
}
|
|
|
|
void cmn(Register src1, const Operand& src2, Condition cond = al);
|
|
|
|
void orr(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
void orr(Register dst, Register src1, Register src2,
|
|
SBit s = LeaveCC, Condition cond = al) {
|
|
orr(dst, src1, Operand(src2), s, cond);
|
|
}
|
|
|
|
void mov(Register dst, const Operand& src,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
void mov(Register dst, Register src, SBit s = LeaveCC, Condition cond = al) {
|
|
mov(dst, Operand(src), s, cond);
|
|
}
|
|
|
|
// ARMv7 instructions for loading a 32 bit immediate in two instructions.
|
|
// This may actually emit a different mov instruction, but on an ARMv7 it
|
|
// is guaranteed to only emit one instruction.
|
|
void movw(Register reg, uint32_t immediate, Condition cond = al);
|
|
// The constant for movt should be in the range 0-0xffff.
|
|
void movt(Register reg, uint32_t immediate, Condition cond = al);
|
|
|
|
void bic(Register dst, Register src1, const Operand& src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void mvn(Register dst, const Operand& src,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
// Multiply instructions
|
|
|
|
void mla(Register dst, Register src1, Register src2, Register srcA,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void mul(Register dst, Register src1, Register src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void smlal(Register dstL, Register dstH, Register src1, Register src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void smull(Register dstL, Register dstH, Register src1, Register src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void umlal(Register dstL, Register dstH, Register src1, Register src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
void umull(Register dstL, Register dstH, Register src1, Register src2,
|
|
SBit s = LeaveCC, Condition cond = al);
|
|
|
|
// Miscellaneous arithmetic instructions
|
|
|
|
void clz(Register dst, Register src, Condition cond = al); // v5 and above
|
|
|
|
// Saturating instructions. v6 and above.
|
|
|
|
// Unsigned saturate.
|
|
//
|
|
// Saturate an optionally shifted signed value to an unsigned range.
|
|
//
|
|
// usat dst, #satpos, src
|
|
// usat dst, #satpos, src, lsl #sh
|
|
// usat dst, #satpos, src, asr #sh
|
|
//
|
|
// Register dst will contain:
|
|
//
|
|
// 0, if s < 0
|
|
// (1 << satpos) - 1, if s > ((1 << satpos) - 1)
|
|
// s, otherwise
|
|
//
|
|
// where s is the contents of src after shifting (if used.)
|
|
void usat(Register dst, int satpos, const Operand& src, Condition cond = al);
|
|
|
|
// Bitfield manipulation instructions. v7 and above.
|
|
|
|
void ubfx(Register dst, Register src, int lsb, int width,
|
|
Condition cond = al);
|
|
|
|
void sbfx(Register dst, Register src, int lsb, int width,
|
|
Condition cond = al);
|
|
|
|
void bfc(Register dst, int lsb, int width, Condition cond = al);
|
|
|
|
void bfi(Register dst, Register src, int lsb, int width,
|
|
Condition cond = al);
|
|
|
|
// Status register access instructions
|
|
|
|
void mrs(Register dst, SRegister s, Condition cond = al);
|
|
void msr(SRegisterFieldMask fields, const Operand& src, Condition cond = al);
|
|
|
|
// Load/Store instructions
|
|
void ldr(Register dst, const MemOperand& src, Condition cond = al);
|
|
void str(Register src, const MemOperand& dst, Condition cond = al);
|
|
void ldrb(Register dst, const MemOperand& src, Condition cond = al);
|
|
void strb(Register src, const MemOperand& dst, Condition cond = al);
|
|
void ldrh(Register dst, const MemOperand& src, Condition cond = al);
|
|
void strh(Register src, const MemOperand& dst, Condition cond = al);
|
|
void ldrsb(Register dst, const MemOperand& src, Condition cond = al);
|
|
void ldrsh(Register dst, const MemOperand& src, Condition cond = al);
|
|
void ldrd(Register dst1,
|
|
Register dst2,
|
|
const MemOperand& src, Condition cond = al);
|
|
void strd(Register src1,
|
|
Register src2,
|
|
const MemOperand& dst, Condition cond = al);
|
|
|
|
// Load/Store multiple instructions
|
|
void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al);
|
|
void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al);
|
|
|
|
// Exception-generating instructions and debugging support
|
|
static const int kDefaultStopCode = -1;
|
|
void stop(const char* msg,
|
|
Condition cond = al,
|
|
int32_t code = kDefaultStopCode);
|
|
|
|
void bkpt(uint32_t imm16); // v5 and above
|
|
void svc(uint32_t imm24, Condition cond = al);
|
|
|
|
// Coprocessor instructions
|
|
|
|
void cdp(Coprocessor coproc, int opcode_1,
|
|
CRegister crd, CRegister crn, CRegister crm,
|
|
int opcode_2, Condition cond = al);
|
|
|
|
void cdp2(Coprocessor coproc, int opcode_1,
|
|
CRegister crd, CRegister crn, CRegister crm,
|
|
int opcode_2); // v5 and above
|
|
|
|
void mcr(Coprocessor coproc, int opcode_1,
|
|
Register rd, CRegister crn, CRegister crm,
|
|
int opcode_2 = 0, Condition cond = al);
|
|
|
|
void mcr2(Coprocessor coproc, int opcode_1,
|
|
Register rd, CRegister crn, CRegister crm,
|
|
int opcode_2 = 0); // v5 and above
|
|
|
|
void mrc(Coprocessor coproc, int opcode_1,
|
|
Register rd, CRegister crn, CRegister crm,
|
|
int opcode_2 = 0, Condition cond = al);
|
|
|
|
void mrc2(Coprocessor coproc, int opcode_1,
|
|
Register rd, CRegister crn, CRegister crm,
|
|
int opcode_2 = 0); // v5 and above
|
|
|
|
void ldc(Coprocessor coproc, CRegister crd, const MemOperand& src,
|
|
LFlag l = Short, Condition cond = al);
|
|
void ldc(Coprocessor coproc, CRegister crd, Register base, int option,
|
|
LFlag l = Short, Condition cond = al);
|
|
|
|
void ldc2(Coprocessor coproc, CRegister crd, const MemOperand& src,
|
|
LFlag l = Short); // v5 and above
|
|
void ldc2(Coprocessor coproc, CRegister crd, Register base, int option,
|
|
LFlag l = Short); // v5 and above
|
|
|
|
void stc(Coprocessor coproc, CRegister crd, const MemOperand& dst,
|
|
LFlag l = Short, Condition cond = al);
|
|
void stc(Coprocessor coproc, CRegister crd, Register base, int option,
|
|
LFlag l = Short, Condition cond = al);
|
|
|
|
void stc2(Coprocessor coproc, CRegister crd, const MemOperand& dst,
|
|
LFlag l = Short); // v5 and above
|
|
void stc2(Coprocessor coproc, CRegister crd, Register base, int option,
|
|
LFlag l = Short); // v5 and above
|
|
|
|
// Support for VFP.
|
|
// All these APIs support S0 to S31 and D0 to D15.
|
|
// Currently these APIs do not support extended D registers, i.e, D16 to D31.
|
|
// However, some simple modifications can allow
|
|
// these APIs to support D16 to D31.
|
|
|
|
void vldr(const DwVfpRegister dst,
|
|
const Register base,
|
|
int offset, // Offset must be a multiple of 4.
|
|
const Condition cond = al);
|
|
|
|
void vldr(const SwVfpRegister dst,
|
|
const Register base,
|
|
int offset, // Offset must be a multiple of 4.
|
|
const Condition cond = al);
|
|
|
|
void vstr(const DwVfpRegister src,
|
|
const Register base,
|
|
int offset, // Offset must be a multiple of 4.
|
|
const Condition cond = al);
|
|
|
|
void vstr(const SwVfpRegister src,
|
|
const Register base,
|
|
int offset, // Offset must be a multiple of 4.
|
|
const Condition cond = al);
|
|
|
|
void vmov(const DwVfpRegister dst,
|
|
double imm,
|
|
const Condition cond = al);
|
|
void vmov(const SwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
const Condition cond = al);
|
|
void vmov(const DwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
const Condition cond = al);
|
|
void vmov(const DwVfpRegister dst,
|
|
const Register src1,
|
|
const Register src2,
|
|
const Condition cond = al);
|
|
void vmov(const Register dst1,
|
|
const Register dst2,
|
|
const DwVfpRegister src,
|
|
const Condition cond = al);
|
|
void vmov(const SwVfpRegister dst,
|
|
const Register src,
|
|
const Condition cond = al);
|
|
void vmov(const Register dst,
|
|
const SwVfpRegister src,
|
|
const Condition cond = al);
|
|
enum ConversionMode {
|
|
FPSCRRounding = 0,
|
|
RoundToZero = 1
|
|
};
|
|
void vcvt_f64_s32(const DwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
ConversionMode mode = RoundToZero,
|
|
const Condition cond = al);
|
|
void vcvt_f32_s32(const SwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
ConversionMode mode = RoundToZero,
|
|
const Condition cond = al);
|
|
void vcvt_f64_u32(const DwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
ConversionMode mode = RoundToZero,
|
|
const Condition cond = al);
|
|
void vcvt_s32_f64(const SwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
ConversionMode mode = RoundToZero,
|
|
const Condition cond = al);
|
|
void vcvt_u32_f64(const SwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
ConversionMode mode = RoundToZero,
|
|
const Condition cond = al);
|
|
void vcvt_f64_f32(const DwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
ConversionMode mode = RoundToZero,
|
|
const Condition cond = al);
|
|
void vcvt_f32_f64(const SwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
ConversionMode mode = RoundToZero,
|
|
const Condition cond = al);
|
|
|
|
void vadd(const DwVfpRegister dst,
|
|
const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond = al);
|
|
void vsub(const DwVfpRegister dst,
|
|
const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond = al);
|
|
void vmul(const DwVfpRegister dst,
|
|
const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond = al);
|
|
void vdiv(const DwVfpRegister dst,
|
|
const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond = al);
|
|
void vcmp(const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond = al);
|
|
void vcmp(const DwVfpRegister src1,
|
|
const double src2,
|
|
const Condition cond = al);
|
|
void vmrs(const Register dst,
|
|
const Condition cond = al);
|
|
void vmsr(const Register dst,
|
|
const Condition cond = al);
|
|
void vsqrt(const DwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
const Condition cond = al);
|
|
|
|
// Pseudo instructions
|
|
|
|
// Different nop operations are used by the code generator to detect certain
|
|
// states of the generated code.
|
|
enum NopMarkerTypes {
|
|
NON_MARKING_NOP = 0,
|
|
DEBUG_BREAK_NOP,
|
|
// IC markers.
|
|
PROPERTY_ACCESS_INLINED,
|
|
PROPERTY_ACCESS_INLINED_CONTEXT,
|
|
PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
|
|
// Helper values.
|
|
LAST_CODE_MARKER,
|
|
FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED
|
|
};
|
|
|
|
void nop(int type = 0); // 0 is the default non-marking type.
|
|
|
|
void push(Register src, Condition cond = al) {
|
|
str(src, MemOperand(sp, 4, NegPreIndex), cond);
|
|
}
|
|
|
|
void pop(Register dst, Condition cond = al) {
|
|
ldr(dst, MemOperand(sp, 4, PostIndex), cond);
|
|
}
|
|
|
|
void pop() {
|
|
add(sp, sp, Operand(kPointerSize));
|
|
}
|
|
|
|
// Jump unconditionally to given label.
|
|
void jmp(Label* L) { b(L, al); }
|
|
|
|
// Check the code size generated from label to here.
|
|
int InstructionsGeneratedSince(Label* l) {
|
|
return (pc_offset() - l->pos()) / kInstrSize;
|
|
}
|
|
|
|
// Check whether an immediate fits an addressing mode 1 instruction.
|
|
bool ImmediateFitsAddrMode1Instruction(int32_t imm32);
|
|
|
|
// Class for scoping postponing the constant pool generation.
|
|
class BlockConstPoolScope {
|
|
public:
|
|
explicit BlockConstPoolScope(Assembler* assem) : assem_(assem) {
|
|
assem_->StartBlockConstPool();
|
|
}
|
|
~BlockConstPoolScope() {
|
|
assem_->EndBlockConstPool();
|
|
}
|
|
|
|
private:
|
|
Assembler* assem_;
|
|
|
|
DISALLOW_IMPLICIT_CONSTRUCTORS(BlockConstPoolScope);
|
|
};
|
|
|
|
// Postpone the generation of the constant pool for the specified number of
|
|
// instructions.
|
|
void BlockConstPoolFor(int instructions);
|
|
|
|
// Debugging
|
|
|
|
// Mark address of the ExitJSFrame code.
|
|
void RecordJSReturn();
|
|
|
|
// Mark address of a debug break slot.
|
|
void RecordDebugBreakSlot();
|
|
|
|
// Record a comment relocation entry that can be used by a disassembler.
|
|
// Use --code-comments to enable.
|
|
void RecordComment(const char* msg);
|
|
|
|
// Writes a single byte or word of data in the code stream. Used
|
|
// for inline tables, e.g., jump-tables. The constant pool should be
|
|
// emitted before any use of db and dd to ensure that constant pools
|
|
// are not emitted as part of the tables generated.
|
|
void db(uint8_t data);
|
|
void dd(uint32_t data);
|
|
|
|
int pc_offset() const { return pc_ - buffer_; }
|
|
|
|
PositionsRecorder* positions_recorder() { return &positions_recorder_; }
|
|
|
|
bool can_peephole_optimize(int instructions) {
|
|
if (!allow_peephole_optimization_) return false;
|
|
if (last_bound_pos_ > pc_offset() - instructions * kInstrSize) return false;
|
|
return reloc_info_writer.last_pc() <= pc_ - instructions * kInstrSize;
|
|
}
|
|
|
|
// Read/patch instructions
|
|
static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
|
|
static void instr_at_put(byte* pc, Instr instr) {
|
|
*reinterpret_cast<Instr*>(pc) = instr;
|
|
}
|
|
static bool IsBranch(Instr instr);
|
|
static int GetBranchOffset(Instr instr);
|
|
static bool IsLdrRegisterImmediate(Instr instr);
|
|
static int GetLdrRegisterImmediateOffset(Instr instr);
|
|
static Instr SetLdrRegisterImmediateOffset(Instr instr, int offset);
|
|
static bool IsStrRegisterImmediate(Instr instr);
|
|
static Instr SetStrRegisterImmediateOffset(Instr instr, int offset);
|
|
static bool IsAddRegisterImmediate(Instr instr);
|
|
static Instr SetAddRegisterImmediateOffset(Instr instr, int offset);
|
|
static Register GetRd(Instr instr);
|
|
static bool IsPush(Instr instr);
|
|
static bool IsPop(Instr instr);
|
|
static bool IsStrRegFpOffset(Instr instr);
|
|
static bool IsLdrRegFpOffset(Instr instr);
|
|
static bool IsStrRegFpNegOffset(Instr instr);
|
|
static bool IsLdrRegFpNegOffset(Instr instr);
|
|
static bool IsLdrPcImmediateOffset(Instr instr);
|
|
static bool IsNop(Instr instr, int type = NON_MARKING_NOP);
|
|
|
|
// Check if is time to emit a constant pool for pending reloc info entries
|
|
void CheckConstPool(bool force_emit, bool require_jump);
|
|
|
|
protected:
|
|
int buffer_space() const { return reloc_info_writer.pos() - pc_; }
|
|
|
|
// Read/patch instructions
|
|
Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
|
|
void instr_at_put(int pos, Instr instr) {
|
|
*reinterpret_cast<Instr*>(buffer_ + pos) = instr;
|
|
}
|
|
|
|
// Decode branch instruction at pos and return branch target pos
|
|
int target_at(int pos);
|
|
|
|
// Patch branch instruction at pos to branch to given branch target pos
|
|
void target_at_put(int pos, int target_pos);
|
|
|
|
// Block the emission of the constant pool before pc_offset
|
|
void BlockConstPoolBefore(int pc_offset) {
|
|
if (no_const_pool_before_ < pc_offset) no_const_pool_before_ = pc_offset;
|
|
}
|
|
|
|
void StartBlockConstPool() {
|
|
const_pool_blocked_nesting_++;
|
|
}
|
|
void EndBlockConstPool() {
|
|
const_pool_blocked_nesting_--;
|
|
}
|
|
bool is_const_pool_blocked() const { return const_pool_blocked_nesting_ > 0; }
|
|
|
|
private:
|
|
// Code buffer:
|
|
// The buffer into which code and relocation info are generated.
|
|
byte* buffer_;
|
|
int buffer_size_;
|
|
// True if the assembler owns the buffer, false if buffer is external.
|
|
bool own_buffer_;
|
|
|
|
// Buffer size and constant pool distance are checked together at regular
|
|
// intervals of kBufferCheckInterval emitted bytes
|
|
static const int kBufferCheckInterval = 1*KB/2;
|
|
int next_buffer_check_; // pc offset of next buffer check
|
|
|
|
// Code generation
|
|
// The relocation writer's position is at least kGap bytes below the end of
|
|
// the generated instructions. This is so that multi-instruction sequences do
|
|
// not have to check for overflow. The same is true for writes of large
|
|
// relocation info entries.
|
|
static const int kGap = 32;
|
|
byte* pc_; // the program counter; moves forward
|
|
|
|
// Constant pool generation
|
|
// Pools are emitted in the instruction stream, preferably after unconditional
|
|
// jumps or after returns from functions (in dead code locations).
|
|
// If a long code sequence does not contain unconditional jumps, it is
|
|
// necessary to emit the constant pool before the pool gets too far from the
|
|
// location it is accessed from. In this case, we emit a jump over the emitted
|
|
// constant pool.
|
|
// Constants in the pool may be addresses of functions that gets relocated;
|
|
// if so, a relocation info entry is associated to the constant pool entry.
|
|
|
|
// Repeated checking whether the constant pool should be emitted is rather
|
|
// expensive. By default we only check again once a number of instructions
|
|
// has been generated. That also means that the sizing of the buffers is not
|
|
// an exact science, and that we rely on some slop to not overrun buffers.
|
|
static const int kCheckConstIntervalInst = 32;
|
|
static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
|
|
|
|
|
|
// Pools are emitted after function return and in dead code at (more or less)
|
|
// regular intervals of kDistBetweenPools bytes
|
|
static const int kDistBetweenPools = 1*KB;
|
|
|
|
// Constants in pools are accessed via pc relative addressing, which can
|
|
// reach +/-4KB thereby defining a maximum distance between the instruction
|
|
// and the accessed constant. We satisfy this constraint by limiting the
|
|
// distance between pools.
|
|
static const int kMaxDistBetweenPools = 4*KB - 2*kBufferCheckInterval;
|
|
|
|
// Emission of the constant pool may be blocked in some code sequences.
|
|
int const_pool_blocked_nesting_; // Block emission if this is not zero.
|
|
int no_const_pool_before_; // Block emission before this pc offset.
|
|
|
|
// Keep track of the last emitted pool to guarantee a maximal distance
|
|
int last_const_pool_end_; // pc offset following the last constant pool
|
|
|
|
// Relocation info generation
|
|
// Each relocation is encoded as a variable size value
|
|
static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
|
|
RelocInfoWriter reloc_info_writer;
|
|
// Relocation info records are also used during code generation as temporary
|
|
// containers for constants and code target addresses until they are emitted
|
|
// to the constant pool. These pending relocation info records are temporarily
|
|
// stored in a separate buffer until a constant pool is emitted.
|
|
// If every instruction in a long sequence is accessing the pool, we need one
|
|
// pending relocation entry per instruction.
|
|
static const int kMaxNumPRInfo = kMaxDistBetweenPools/kInstrSize;
|
|
RelocInfo prinfo_[kMaxNumPRInfo]; // the buffer of pending relocation info
|
|
int num_prinfo_; // number of pending reloc info entries in the buffer
|
|
|
|
// The bound position, before this we cannot do instruction elimination.
|
|
int last_bound_pos_;
|
|
|
|
// Code emission
|
|
inline void CheckBuffer();
|
|
void GrowBuffer();
|
|
inline void emit(Instr x);
|
|
|
|
// Instruction generation
|
|
void addrmod1(Instr instr, Register rn, Register rd, const Operand& x);
|
|
void addrmod2(Instr instr, Register rd, const MemOperand& x);
|
|
void addrmod3(Instr instr, Register rd, const MemOperand& x);
|
|
void addrmod4(Instr instr, Register rn, RegList rl);
|
|
void addrmod5(Instr instr, CRegister crd, const MemOperand& x);
|
|
|
|
// Labels
|
|
void print(Label* L);
|
|
void bind_to(Label* L, int pos);
|
|
void link_to(Label* L, Label* appendix);
|
|
void next(Label* L);
|
|
|
|
// Record reloc info for current pc_
|
|
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
|
|
|
|
friend class RegExpMacroAssemblerARM;
|
|
friend class RelocInfo;
|
|
friend class CodePatcher;
|
|
friend class BlockConstPoolScope;
|
|
|
|
PositionsRecorder positions_recorder_;
|
|
bool allow_peephole_optimization_;
|
|
friend class PositionsRecorder;
|
|
friend class EnsureSpace;
|
|
};
|
|
|
|
|
|
class EnsureSpace BASE_EMBEDDED {
|
|
public:
|
|
explicit EnsureSpace(Assembler* assembler) {
|
|
assembler->CheckBuffer();
|
|
}
|
|
};
|
|
|
|
|
|
} } // namespace v8::internal
|
|
|
|
#endif // V8_ARM_ASSEMBLER_ARM_H_
|