9ff644ae67
The stack check instruction sequence is pattern-matched in
instruction-selector-{ia32,x64}.cc and replaced with its own specialized
opcode, for which we later generate an efficient stack check in a single
instruction.
But this pattern matching has never worked for CSA-generated code. The
matcher expected LoadStackPointer in the right operand and the external
reference load in the left operand. CSA generated exactly vice-versa.
This CL does a few things; it
1. reverts the recent change to load the
limit from smi roots:
Revert "[csa] Load the stack limit from smi roots"
This reverts commit 507c29c940.
2. tweaks the CSA instruction sequence to output what the matcher
expects.
3. refactors stack check matching into a new StackCheckMatcher class.
4. typifies CSA::PerformStackCheck as a drive-by.
Bug: v8:6666,v8:7844
Change-Id: I9bb879ac10bfe7187750c5f9e7834dc4accf28b5
Reviewed-on: https://chromium-review.googlesource.com/1099068
Reviewed-by: Leszek Swirski <leszeks@chromium.org>
Reviewed-by: Sigurd Schneider <sigurds@chromium.org>
Reviewed-by: Jaroslav Sevcik <jarin@chromium.org>
Commit-Queue: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#53737}
1689 lines
60 KiB
C++
1689 lines
60 KiB
C++
// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#include "test/unittests/compiler/instruction-selector-unittest.h"
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#include "src/compiler/node-matchers.h"
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#include "src/objects-inl.h"
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namespace v8 {
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namespace internal {
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namespace compiler {
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// -----------------------------------------------------------------------------
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// Conversions.
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TEST_F(InstructionSelectorTest, ChangeFloat32ToFloat64WithParameter) {
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StreamBuilder m(this, MachineType::Float32(), MachineType::Float64());
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m.Return(m.ChangeFloat32ToFloat64(m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kSSEFloat32ToFloat64, s[0]->arch_opcode());
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EXPECT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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TEST_F(InstructionSelectorTest, ChangeInt32ToInt64WithParameter) {
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StreamBuilder m(this, MachineType::Int64(), MachineType::Int32());
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m.Return(m.ChangeInt32ToInt64(m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kX64Movsxlq, s[0]->arch_opcode());
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}
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TEST_F(InstructionSelectorTest, ChangeUint32ToFloat64WithParameter) {
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StreamBuilder m(this, MachineType::Float64(), MachineType::Uint32());
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m.Return(m.ChangeUint32ToFloat64(m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kSSEUint32ToFloat64, s[0]->arch_opcode());
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}
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TEST_F(InstructionSelectorTest, ChangeUint32ToUint64WithParameter) {
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StreamBuilder m(this, MachineType::Uint64(), MachineType::Uint32());
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m.Return(m.ChangeUint32ToUint64(m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kX64Movl, s[0]->arch_opcode());
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}
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TEST_F(InstructionSelectorTest, TruncateFloat64ToFloat32WithParameter) {
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StreamBuilder m(this, MachineType::Float64(), MachineType::Float32());
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m.Return(m.TruncateFloat64ToFloat32(m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kSSEFloat64ToFloat32, s[0]->arch_opcode());
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EXPECT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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TEST_F(InstructionSelectorTest, TruncateInt64ToInt32WithParameter) {
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StreamBuilder m(this, MachineType::Int32(), MachineType::Int64());
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m.Return(m.TruncateInt64ToInt32(m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kX64Movl, s[0]->arch_opcode());
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}
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namespace {
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struct LoadWithToInt64Extension {
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MachineType type;
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ArchOpcode expected_opcode;
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};
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std::ostream& operator<<(std::ostream& os,
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const LoadWithToInt64Extension& i32toi64) {
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return os << i32toi64.type;
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}
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static const LoadWithToInt64Extension kLoadWithToInt64Extensions[] = {
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{MachineType::Int8(), kX64Movsxbq},
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{MachineType::Uint8(), kX64Movzxbq},
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{MachineType::Int16(), kX64Movsxwq},
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{MachineType::Uint16(), kX64Movzxwq},
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{MachineType::Int32(), kX64Movsxlq}};
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} // namespace
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typedef InstructionSelectorTestWithParam<LoadWithToInt64Extension>
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InstructionSelectorChangeInt32ToInt64Test;
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TEST_P(InstructionSelectorChangeInt32ToInt64Test, ChangeInt32ToInt64WithLoad) {
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const LoadWithToInt64Extension extension = GetParam();
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StreamBuilder m(this, MachineType::Int64(), MachineType::Pointer());
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m.Return(m.ChangeInt32ToInt64(m.Load(extension.type, m.Parameter(0))));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(extension.expected_opcode, s[0]->arch_opcode());
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
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InstructionSelectorChangeInt32ToInt64Test,
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::testing::ValuesIn(kLoadWithToInt64Extensions));
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// -----------------------------------------------------------------------------
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// Loads and stores
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namespace {
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struct MemoryAccess {
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MachineType type;
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ArchOpcode load_opcode;
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ArchOpcode store_opcode;
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};
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std::ostream& operator<<(std::ostream& os, const MemoryAccess& memacc) {
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return os << memacc.type;
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}
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static const MemoryAccess kMemoryAccesses[] = {
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{MachineType::Int8(), kX64Movsxbl, kX64Movb},
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{MachineType::Uint8(), kX64Movzxbl, kX64Movb},
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{MachineType::Int16(), kX64Movsxwl, kX64Movw},
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{MachineType::Uint16(), kX64Movzxwl, kX64Movw},
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{MachineType::Int32(), kX64Movl, kX64Movl},
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{MachineType::Uint32(), kX64Movl, kX64Movl},
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{MachineType::Int64(), kX64Movq, kX64Movq},
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{MachineType::Uint64(), kX64Movq, kX64Movq},
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{MachineType::Float32(), kX64Movss, kX64Movss},
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{MachineType::Float64(), kX64Movsd, kX64Movsd}};
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} // namespace
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typedef InstructionSelectorTestWithParam<MemoryAccess>
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InstructionSelectorMemoryAccessTest;
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TEST_P(InstructionSelectorMemoryAccessTest, LoadWithParameters) {
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const MemoryAccess memacc = GetParam();
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StreamBuilder m(this, memacc.type, MachineType::Pointer(),
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MachineType::Int32());
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m.Return(m.Load(memacc.type, m.Parameter(0), m.Parameter(1)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) {
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const MemoryAccess memacc = GetParam();
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StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer(),
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MachineType::Int32(), memacc.type);
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m.Store(memacc.type.representation(), m.Parameter(0), m.Parameter(1),
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m.Parameter(2), kNoWriteBarrier);
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m.Return(m.Int32Constant(0));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
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EXPECT_EQ(3U, s[0]->InputCount());
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EXPECT_EQ(0U, s[0]->OutputCount());
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
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InstructionSelectorMemoryAccessTest,
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::testing::ValuesIn(kMemoryAccesses));
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// -----------------------------------------------------------------------------
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// ChangeUint32ToUint64.
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namespace {
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typedef Node* (RawMachineAssembler::*Constructor)(Node*, Node*);
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struct BinaryOperation {
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Constructor constructor;
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const char* constructor_name;
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};
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std::ostream& operator<<(std::ostream& os, const BinaryOperation& bop) {
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return os << bop.constructor_name;
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}
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const BinaryOperation kWord32BinaryOperations[] = {
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{&RawMachineAssembler::Word32And, "Word32And"},
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{&RawMachineAssembler::Word32Or, "Word32Or"},
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{&RawMachineAssembler::Word32Xor, "Word32Xor"},
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{&RawMachineAssembler::Word32Shl, "Word32Shl"},
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{&RawMachineAssembler::Word32Shr, "Word32Shr"},
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{&RawMachineAssembler::Word32Sar, "Word32Sar"},
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{&RawMachineAssembler::Word32Ror, "Word32Ror"},
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{&RawMachineAssembler::Word32Equal, "Word32Equal"},
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{&RawMachineAssembler::Int32Add, "Int32Add"},
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{&RawMachineAssembler::Int32Sub, "Int32Sub"},
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{&RawMachineAssembler::Int32Mul, "Int32Mul"},
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{&RawMachineAssembler::Int32MulHigh, "Int32MulHigh"},
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{&RawMachineAssembler::Int32Div, "Int32Div"},
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{&RawMachineAssembler::Int32LessThan, "Int32LessThan"},
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{&RawMachineAssembler::Int32LessThanOrEqual, "Int32LessThanOrEqual"},
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{&RawMachineAssembler::Int32Mod, "Int32Mod"},
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{&RawMachineAssembler::Uint32Div, "Uint32Div"},
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{&RawMachineAssembler::Uint32LessThan, "Uint32LessThan"},
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{&RawMachineAssembler::Uint32LessThanOrEqual, "Uint32LessThanOrEqual"},
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{&RawMachineAssembler::Uint32Mod, "Uint32Mod"}};
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} // namespace
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typedef InstructionSelectorTestWithParam<BinaryOperation>
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InstructionSelectorChangeUint32ToUint64Test;
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TEST_P(InstructionSelectorChangeUint32ToUint64Test, ChangeUint32ToUint64) {
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const BinaryOperation& bop = GetParam();
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StreamBuilder m(this, MachineType::Uint64(), MachineType::Int32(),
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MachineType::Int32());
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Node* const p0 = m.Parameter(0);
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Node* const p1 = m.Parameter(1);
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m.Return(m.ChangeUint32ToUint64((m.*bop.constructor)(p0, p1)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
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InstructionSelectorChangeUint32ToUint64Test,
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::testing::ValuesIn(kWord32BinaryOperations));
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// -----------------------------------------------------------------------------
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// CanElideChangeUint32ToUint64
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namespace {
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template <typename T>
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struct MachInst {
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T constructor;
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const char* constructor_name;
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ArchOpcode arch_opcode;
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MachineType machine_type;
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};
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typedef MachInst<Node* (RawMachineAssembler::*)(Node*, Node*)> MachInst2;
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// X64 instructions that clear the top 32 bits of the destination.
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const MachInst2 kCanElideChangeUint32ToUint64[] = {
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{&RawMachineAssembler::Word32And, "Word32And", kX64And32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Word32Or, "Word32Or", kX64Or32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Word32Xor, "Word32Xor", kX64Xor32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Word32Shl, "Word32Shl", kX64Shl32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Word32Shr, "Word32Shr", kX64Shr32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Word32Sar, "Word32Sar", kX64Sar32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Word32Ror, "Word32Ror", kX64Ror32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Word32Equal, "Word32Equal", kX64Cmp32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Int32Add, "Int32Add", kX64Lea32,
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MachineType::Int32()},
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{&RawMachineAssembler::Int32Sub, "Int32Sub", kX64Sub32,
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MachineType::Int32()},
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{&RawMachineAssembler::Int32Mul, "Int32Mul", kX64Imul32,
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MachineType::Int32()},
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{&RawMachineAssembler::Int32MulHigh, "Int32MulHigh", kX64ImulHigh32,
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MachineType::Int32()},
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{&RawMachineAssembler::Int32Div, "Int32Div", kX64Idiv32,
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MachineType::Int32()},
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{&RawMachineAssembler::Int32LessThan, "Int32LessThan", kX64Cmp32,
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MachineType::Int32()},
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{&RawMachineAssembler::Int32LessThanOrEqual, "Int32LessThanOrEqual",
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kX64Cmp32, MachineType::Int32()},
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{&RawMachineAssembler::Int32Mod, "Int32Mod", kX64Idiv32,
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MachineType::Int32()},
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{&RawMachineAssembler::Uint32Div, "Uint32Div", kX64Udiv32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Uint32LessThan, "Uint32LessThan", kX64Cmp32,
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MachineType::Uint32()},
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{&RawMachineAssembler::Uint32LessThanOrEqual, "Uint32LessThanOrEqual",
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kX64Cmp32, MachineType::Uint32()},
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{&RawMachineAssembler::Uint32Mod, "Uint32Mod", kX64Udiv32,
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MachineType::Uint32()},
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};
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} // namespace
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typedef InstructionSelectorTestWithParam<MachInst2>
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InstructionSelectorElidedChangeUint32ToUint64Test;
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TEST_P(InstructionSelectorElidedChangeUint32ToUint64Test, Parameter) {
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const MachInst2 binop = GetParam();
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StreamBuilder m(this, MachineType::Uint64(), binop.machine_type,
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binop.machine_type);
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m.Return(m.ChangeUint32ToUint64(
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(m.*binop.constructor)(m.Parameter(0), m.Parameter(1))));
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Stream s = m.Build();
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// Make sure the `ChangeUint32ToUint64` node turned into a no-op.
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(binop.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
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InstructionSelectorElidedChangeUint32ToUint64Test,
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::testing::ValuesIn(kCanElideChangeUint32ToUint64));
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// ChangeUint32ToUint64AfterLoad
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TEST_F(InstructionSelectorTest, ChangeUint32ToUint64AfterLoad) {
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// For each case, make sure the `ChangeUint32ToUint64` node turned into a
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// no-op.
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// movzxbl
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{
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StreamBuilder m(this, MachineType::Uint64(), MachineType::Pointer(),
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MachineType::Int32());
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m.Return(m.ChangeUint32ToUint64(
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m.Load(MachineType::Uint8(), m.Parameter(0), m.Parameter(1))));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kX64Movzxbl, s[0]->arch_opcode());
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EXPECT_EQ(kMode_MR1, s[0]->addressing_mode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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// movsxbl
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{
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StreamBuilder m(this, MachineType::Uint64(), MachineType::Pointer(),
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MachineType::Int32());
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m.Return(m.ChangeUint32ToUint64(
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m.Load(MachineType::Int8(), m.Parameter(0), m.Parameter(1))));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kX64Movsxbl, s[0]->arch_opcode());
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EXPECT_EQ(kMode_MR1, s[0]->addressing_mode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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// movzxwl
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{
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StreamBuilder m(this, MachineType::Uint64(), MachineType::Pointer(),
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MachineType::Int32());
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m.Return(m.ChangeUint32ToUint64(
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m.Load(MachineType::Uint16(), m.Parameter(0), m.Parameter(1))));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kX64Movzxwl, s[0]->arch_opcode());
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EXPECT_EQ(kMode_MR1, s[0]->addressing_mode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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// movsxwl
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{
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StreamBuilder m(this, MachineType::Uint64(), MachineType::Pointer(),
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MachineType::Int32());
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m.Return(m.ChangeUint32ToUint64(
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m.Load(MachineType::Int16(), m.Parameter(0), m.Parameter(1))));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kX64Movsxwl, s[0]->arch_opcode());
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EXPECT_EQ(kMode_MR1, s[0]->addressing_mode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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}
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// -----------------------------------------------------------------------------
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// TruncateInt64ToInt32.
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TEST_F(InstructionSelectorTest, TruncateInt64ToInt32WithWord64Sar) {
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StreamBuilder m(this, MachineType::Int32(), MachineType::Int64());
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Node* const p = m.Parameter(0);
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Node* const t = m.TruncateInt64ToInt32(m.Word64Sar(p, m.Int64Constant(32)));
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m.Return(t);
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kX64Shr, s[0]->arch_opcode());
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ASSERT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(s.ToVreg(p), s.ToVreg(s[0]->InputAt(0)));
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EXPECT_EQ(32, s.ToInt32(s[0]->InputAt(1)));
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_TRUE(s.IsSameAsFirst(s[0]->OutputAt(0)));
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EXPECT_EQ(s.ToVreg(t), s.ToVreg(s[0]->OutputAt(0)));
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}
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TEST_F(InstructionSelectorTest, TruncateInt64ToInt32WithWord64Shr) {
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StreamBuilder m(this, MachineType::Int32(), MachineType::Int64());
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Node* const p = m.Parameter(0);
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Node* const t = m.TruncateInt64ToInt32(m.Word64Shr(p, m.Int64Constant(32)));
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m.Return(t);
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kX64Shr, s[0]->arch_opcode());
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ASSERT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(s.ToVreg(p), s.ToVreg(s[0]->InputAt(0)));
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EXPECT_EQ(32, s.ToInt32(s[0]->InputAt(1)));
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ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_TRUE(s.IsSameAsFirst(s[0]->OutputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(t), s.ToVreg(s[0]->OutputAt(0)));
|
|
}
|
|
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// Addition.
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddWithInt32ParametersLea) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const a0 = m.Int32Add(p0, p1);
|
|
// Additional uses of input to add chooses lea
|
|
Node* const a1 = m.Int32Div(p0, p1);
|
|
m.Return(m.Int32Div(a0, a1));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(3U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddConstantAsLeaSingle) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c0 = m.Int32Constant(15);
|
|
// If one of the add's operands is only used once, use an "leal", even though
|
|
// an "addl" could be used. The "leal" has proven faster--out best guess is
|
|
// that it gives the register allocation more freedom and it doesn't set
|
|
// flags, reducing pressure in the CPU's pipeline. If we're lucky with
|
|
// register allocation, then code generation will select an "addl" later for
|
|
// the cases that have been measured to be faster.
|
|
Node* const v0 = m.Int32Add(p0, c0);
|
|
m.Return(v0);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddConstantAsAdd) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c0 = m.Int32Constant(1);
|
|
// If there is only a single use of an add's input and the immediate constant
|
|
// for the add is 1, don't use an inc. It is much slower on modern Intel
|
|
// architectures.
|
|
m.Return(m.Int32Add(p0, c0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddConstantAsLeaDouble) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c0 = m.Int32Constant(15);
|
|
// A second use of an add's input uses lea
|
|
Node* const a0 = m.Int32Add(p0, c0);
|
|
m.Return(m.Int32Div(a0, p0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(2U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddCommutedConstantAsLeaSingle) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c0 = m.Int32Constant(15);
|
|
// If one of the add's operands is only used once, use an "leal", even though
|
|
// an "addl" could be used. The "leal" has proven faster--out best guess is
|
|
// that it gives the register allocation more freedom and it doesn't set
|
|
// flags, reducing pressure in the CPU's pipeline. If we're lucky with
|
|
// register allocation, then code generation will select an "addl" later for
|
|
// the cases that have been measured to be faster.
|
|
m.Return(m.Int32Add(c0, p0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddCommutedConstantAsLeaDouble) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c0 = m.Int32Constant(15);
|
|
// A second use of an add's input uses lea
|
|
Node* const a0 = m.Int32Add(c0, p0);
|
|
USE(a0);
|
|
m.Return(m.Int32Div(a0, p0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(2U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddSimpleAsAdd) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
// If one of the add's operands is only used once, use an "leal", even though
|
|
// an "addl" could be used. The "leal" has proven faster--out best guess is
|
|
// that it gives the register allocation more freedom and it doesn't set
|
|
// flags, reducing pressure in the CPU's pipeline. If we're lucky with
|
|
// register allocation, then code generation will select an "addl" later for
|
|
// the cases that have been measured to be faster.
|
|
m.Return(m.Int32Add(p0, p1));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR1, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddSimpleAsLea) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
// If all of of the add's operands are used multiple times, use an "leal".
|
|
Node* const v1 = m.Int32Add(p0, p1);
|
|
m.Return(m.Int32Add(m.Int32Add(v1, p1), p0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(3U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR1, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2Mul) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(2));
|
|
m.Return(m.Int32Add(p0, s0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddCommutedScaled2Mul) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(2));
|
|
m.Return(m.Int32Add(s0, p0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2Shl) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Word32Shl(p1, m.Int32Constant(1));
|
|
m.Return(m.Int32Add(p0, s0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddCommutedScaled2Shl) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Word32Shl(p1, m.Int32Constant(1));
|
|
m.Return(m.Int32Add(s0, p0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled4Mul) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(4));
|
|
m.Return(m.Int32Add(p0, s0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR4, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled4Shl) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Word32Shl(p1, m.Int32Constant(2));
|
|
m.Return(m.Int32Add(p0, s0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR4, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled8Mul) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(8));
|
|
m.Return(m.Int32Add(p0, s0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR8, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled8Shl) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Word32Shl(p1, m.Int32Constant(3));
|
|
m.Return(m.Int32Add(p0, s0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR8, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2MulWithConstant) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(2));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(c0, m.Int32Add(p0, s0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2MulWithConstantShuffle1) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(2));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(p0, m.Int32Add(s0, c0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2MulWithConstantShuffle2) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(2));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(s0, m.Int32Add(c0, p0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2MulWithConstantShuffle3) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(2));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(m.Int32Add(s0, c0), p0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2MulWithConstantShuffle4) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(2));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(m.Int32Add(c0, p0), s0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2MulWithConstantShuffle5) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(2));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(m.Int32Add(p0, s0), c0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2ShlWithConstant) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Word32Shl(p1, m.Int32Constant(1));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(c0, m.Int32Add(p0, s0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled4MulWithConstant) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(4));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(c0, m.Int32Add(p0, s0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR4I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled4ShlWithConstant) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Word32Shl(p1, m.Int32Constant(2));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(c0, m.Int32Add(p0, s0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR4I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled8MulWithConstant) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(8));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(c0, m.Int32Add(p0, s0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR8I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled8ShlWithConstant) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const s0 = m.Word32Shl(p1, m.Int32Constant(3));
|
|
Node* const c0 = m.Int32Constant(15);
|
|
m.Return(m.Int32Add(c0, m.Int32Add(p0, s0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR8I, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(s[0]->InputAt(2)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32SubConstantAsSub) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c0 = m.Int32Constant(-1);
|
|
// If there is only a single use of on of the sub's non-constant input, use a
|
|
// "subl" instruction.
|
|
m.Return(m.Int32Sub(p0, c0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32SubConstantAsLea) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c0 = m.Int32Constant(-1);
|
|
// If there are multiple uses of on of the sub's non-constant input, use a
|
|
// "leal" instruction.
|
|
Node* const v0 = m.Int32Sub(p0, c0);
|
|
m.Return(m.Int32Div(p0, v0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(2U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32AddScaled2Other) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const p2 = m.Parameter(2);
|
|
Node* const s0 = m.Int32Mul(p1, m.Int32Constant(2));
|
|
Node* const a0 = m.Int32Add(s0, p2);
|
|
Node* const a1 = m.Int32Add(p0, a0);
|
|
m.Return(a1);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(2U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_EQ(s.ToVreg(a0), s.ToVreg(s[0]->OutputAt(0)));
|
|
ASSERT_EQ(2U, s[1]->InputCount());
|
|
EXPECT_EQ(kX64Lea32, s[1]->arch_opcode());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[1]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(a0), s.ToVreg(s[1]->InputAt(1)));
|
|
EXPECT_EQ(s.ToVreg(a1), s.ToVreg(s[1]->OutputAt(0)));
|
|
}
|
|
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// Multiplication.
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32MulWithInt32MulWithParameters) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const m0 = m.Int32Mul(p0, p1);
|
|
m.Return(m.Int32Mul(m0, p0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(2U, s.size());
|
|
EXPECT_EQ(kX64Imul32, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(m0), s.ToVreg(s[0]->OutputAt(0)));
|
|
EXPECT_EQ(kX64Imul32, s[1]->arch_opcode());
|
|
ASSERT_EQ(2U, s[1]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[1]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(m0), s.ToVreg(s[1]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32MulHigh) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const n = m.Int32MulHigh(p0, p1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64ImulHigh32, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_TRUE(s.IsFixed(s[0]->InputAt(0), rax));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(!s.IsUsedAtStart(s[0]->InputAt(1)));
|
|
ASSERT_LE(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_TRUE(s.IsFixed(s[0]->OutputAt(0), rdx));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Uint32MulHigh) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const n = m.Uint32MulHigh(p0, p1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64UmulHigh32, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_TRUE(s.IsFixed(s[0]->InputAt(0), rax));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_TRUE(!s.IsUsedAtStart(s[0]->InputAt(1)));
|
|
ASSERT_LE(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_TRUE(s.IsFixed(s[0]->OutputAt(0), rdx));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32Mul2BecomesLea) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c1 = m.Int32Constant(2);
|
|
Node* const n = m.Int32Mul(p0, c1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR1, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32Mul3BecomesLea) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c1 = m.Int32Constant(3);
|
|
Node* const n = m.Int32Mul(p0, c1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR2, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32Mul4BecomesLea) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c1 = m.Int32Constant(4);
|
|
Node* const n = m.Int32Mul(p0, c1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_M4, s[0]->addressing_mode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32Mul5BecomesLea) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c1 = m.Int32Constant(5);
|
|
Node* const n = m.Int32Mul(p0, c1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR4, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32Mul8BecomesLea) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c1 = m.Int32Constant(8);
|
|
Node* const n = m.Int32Mul(p0, c1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_M8, s[0]->addressing_mode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32Mul9BecomesLea) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c1 = m.Int32Constant(9);
|
|
Node* const n = m.Int32Mul(p0, c1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR8, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// Word32Shl.
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32Shl1BecomesLea) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c1 = m.Int32Constant(1);
|
|
Node* const n = m.Word32Shl(p0, c1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MR1, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32Shl2BecomesLea) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c1 = m.Int32Constant(2);
|
|
Node* const n = m.Word32Shl(p0, c1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_M4, s[0]->addressing_mode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Int32Shl4BecomesLea) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32(),
|
|
MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const c1 = m.Int32Constant(3);
|
|
Node* const n = m.Word32Shl(p0, c1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lea32, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_M8, s[0]->addressing_mode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
}
|
|
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// Binops with a memory operand.
|
|
|
|
TEST_F(InstructionSelectorTest, LoadAnd32) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Word32And(p0, m.Load(MachineType::Int32(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64And32, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadOr32) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Word32Or(p0, m.Load(MachineType::Int32(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Or32, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadXor32) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Word32Xor(p0, m.Load(MachineType::Int32(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Xor32, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadAdd32) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Int32Add(p0, m.Load(MachineType::Int32(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
// Use lea instead of add, so memory operand is invalid.
|
|
ASSERT_EQ(2U, s.size());
|
|
EXPECT_EQ(kX64Movl, s[0]->arch_opcode());
|
|
EXPECT_EQ(kX64Lea32, s[1]->arch_opcode());
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadSub32) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
|
|
MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Int32Sub(p0, m.Load(MachineType::Int32(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Sub32, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadAnd64) {
|
|
StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
|
|
MachineType::Int64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Word64And(p0, m.Load(MachineType::Int64(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64And, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadOr64) {
|
|
StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
|
|
MachineType::Int64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Word64Or(p0, m.Load(MachineType::Int64(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Or, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadXor64) {
|
|
StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
|
|
MachineType::Int64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Word64Xor(p0, m.Load(MachineType::Int64(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Xor, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadAdd64) {
|
|
StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
|
|
MachineType::Int64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Int64Add(p0, m.Load(MachineType::Int64(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
// Use lea instead of add, so memory operand is invalid.
|
|
ASSERT_EQ(2U, s.size());
|
|
EXPECT_EQ(kX64Movq, s[0]->arch_opcode());
|
|
EXPECT_EQ(kX64Lea, s[1]->arch_opcode());
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadSub64) {
|
|
StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
|
|
MachineType::Int64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
m.Return(
|
|
m.Int64Sub(p0, m.Load(MachineType::Int64(), p1, m.Int32Constant(127))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Sub, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
}
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// Floating point operations.
|
|
|
|
TEST_F(InstructionSelectorTest, Float32Abs) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Float32Abs(p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kSSEFloat32Abs, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_TRUE(s.IsSameAsFirst(s[0]->Output()));
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Float32Abs(p0);
|
|
m.Return(n);
|
|
Stream s = m.Build(AVX);
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kAVXFloat32Abs, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Float64Abs) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Float64Abs(p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kSSEFloat64Abs, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_TRUE(s.IsSameAsFirst(s[0]->Output()));
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Float64Abs(p0);
|
|
m.Return(n);
|
|
Stream s = m.Build(AVX);
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kAVXFloat64Abs, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Float64BinopArithmetic) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
|
MachineType::Float64());
|
|
Node* add = m.Float64Add(m.Parameter(0), m.Parameter(1));
|
|
Node* mul = m.Float64Mul(add, m.Parameter(1));
|
|
Node* sub = m.Float64Sub(mul, add);
|
|
Node* ret = m.Float64Div(mul, sub);
|
|
m.Return(ret);
|
|
Stream s = m.Build(AVX);
|
|
ASSERT_EQ(4U, s.size());
|
|
EXPECT_EQ(kAVXFloat64Add, s[0]->arch_opcode());
|
|
EXPECT_EQ(kAVXFloat64Mul, s[1]->arch_opcode());
|
|
EXPECT_EQ(kAVXFloat64Sub, s[2]->arch_opcode());
|
|
EXPECT_EQ(kAVXFloat64Div, s[3]->arch_opcode());
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
|
MachineType::Float64());
|
|
Node* add = m.Float64Add(m.Parameter(0), m.Parameter(1));
|
|
Node* mul = m.Float64Mul(add, m.Parameter(1));
|
|
Node* sub = m.Float64Sub(mul, add);
|
|
Node* ret = m.Float64Div(mul, sub);
|
|
m.Return(ret);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(4U, s.size());
|
|
EXPECT_EQ(kSSEFloat64Add, s[0]->arch_opcode());
|
|
EXPECT_EQ(kSSEFloat64Mul, s[1]->arch_opcode());
|
|
EXPECT_EQ(kSSEFloat64Sub, s[2]->arch_opcode());
|
|
EXPECT_EQ(kSSEFloat64Div, s[3]->arch_opcode());
|
|
}
|
|
}
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// Miscellaneous.
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Word64ShlWithChangeInt32ToInt64) {
|
|
TRACED_FORRANGE(int64_t, x, 32, 63) {
|
|
StreamBuilder m(this, MachineType::Int64(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Word64Shl(m.ChangeInt32ToInt64(p0), m.Int64Constant(x));
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Shl, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(x, s.ToInt32(s[0]->InputAt(1)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_TRUE(s.IsSameAsFirst(s[0]->Output()));
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Word64ShlWithChangeUint32ToUint64) {
|
|
TRACED_FORRANGE(int64_t, x, 32, 63) {
|
|
StreamBuilder m(this, MachineType::Int64(), MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Word64Shl(m.ChangeUint32ToUint64(p0), m.Int64Constant(x));
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Shl, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(x, s.ToInt32(s[0]->InputAt(1)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_TRUE(s.IsSameAsFirst(s[0]->Output()));
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, Word32AndWith0xFF) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Word32And(p0, m.Int32Constant(0xFF));
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Movzxbl, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Word32And(m.Int32Constant(0xFF), p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Movzxbl, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, Word32AndWith0xFFFF) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Word32And(p0, m.Int32Constant(0xFFFF));
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Movzxwl, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Word32And(m.Int32Constant(0xFFFF), p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Movzxwl, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Word32Clz) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Word32Clz(p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Lzcnt32, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, LoadAndWord64ShiftRight32) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Uint64(), MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const load = m.Load(MachineType::Uint64(), p0);
|
|
Node* const shift = m.Word64Shr(load, m.Int32Constant(32));
|
|
m.Return(shift);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Movl, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(4, s.ToInt32(s[0]->InputAt(1)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(shift), s.ToVreg(s[0]->Output()));
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Int64(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const load = m.Load(MachineType::Int64(), p0);
|
|
Node* const shift = m.Word64Sar(load, m.Int32Constant(32));
|
|
m.Return(shift);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Movsxlq, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(4, s.ToInt32(s[0]->InputAt(1)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(shift), s.ToVreg(s[0]->Output()));
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Int64(), MachineType::Int32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const load = m.Load(MachineType::Int64(), p0);
|
|
Node* const shift = m.Word64Sar(load, m.Int32Constant(32));
|
|
Node* const truncate = m.TruncateInt64ToInt32(shift);
|
|
m.Return(truncate);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Movl, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(4, s.ToInt32(s[0]->InputAt(1)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(shift), s.ToVreg(s[0]->Output()));
|
|
}
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, SpeculationFence) {
|
|
StreamBuilder m(this, MachineType::Int32());
|
|
m.SpeculationFence();
|
|
m.Return(m.Int32Constant(0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kLFence, s[0]->arch_opcode());
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, StackCheck0) {
|
|
ExternalReference js_stack_limit =
|
|
ExternalReference::Create(isolate()->stack_guard()->address_of_jslimit());
|
|
StreamBuilder m(this, MachineType::Int32());
|
|
Node* const sp = m.LoadStackPointer();
|
|
Node* const stack_limit =
|
|
m.Load(MachineType::Pointer(), m.ExternalConstant(js_stack_limit));
|
|
Node* const interrupt = m.UintPtrLessThan(sp, stack_limit);
|
|
|
|
RawMachineLabel if_true, if_false;
|
|
m.Branch(interrupt, &if_true, &if_false);
|
|
|
|
m.Bind(&if_true);
|
|
m.Return(m.Int32Constant(1));
|
|
|
|
m.Bind(&if_false);
|
|
m.Return(m.Int32Constant(0));
|
|
|
|
Stream s = m.Build();
|
|
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64Cmp, s[0]->arch_opcode());
|
|
EXPECT_EQ(4U, s[0]->InputCount());
|
|
EXPECT_EQ(0U, s[0]->OutputCount());
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, StackCheck1) {
|
|
ExternalReference js_stack_limit =
|
|
ExternalReference::Create(isolate()->stack_guard()->address_of_jslimit());
|
|
StreamBuilder m(this, MachineType::Int32());
|
|
Node* const sp = m.LoadStackPointer();
|
|
Node* const stack_limit =
|
|
m.Load(MachineType::Pointer(), m.ExternalConstant(js_stack_limit));
|
|
Node* const sp_within_limit = m.UintPtrLessThan(stack_limit, sp);
|
|
|
|
RawMachineLabel if_true, if_false;
|
|
m.Branch(sp_within_limit, &if_true, &if_false);
|
|
|
|
m.Bind(&if_true);
|
|
m.Return(m.Int32Constant(1));
|
|
|
|
m.Bind(&if_false);
|
|
m.Return(m.Int32Constant(0));
|
|
|
|
Stream s = m.Build();
|
|
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kX64StackCheck, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(0U, s[0]->OutputCount());
|
|
}
|
|
|
|
} // namespace compiler
|
|
} // namespace internal
|
|
} // namespace v8
|