c255fba681
R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/18575003 Patch from Haitao Feng <haitao.feng@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15500 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
171 lines
7.6 KiB
C++
171 lines
7.6 KiB
C++
// Copyright 2010 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The routines exported by this module are subtle. If you use them, even if
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// you get the code right, it will depend on careful reasoning about atomicity
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// and memory ordering; it will be less readable, and harder to maintain. If
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// you plan to use these routines, you should have a good reason, such as solid
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// evidence that performance would otherwise suffer, or there being no
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// alternative. You should assume only properties explicitly guaranteed by the
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// specifications in this file. You are almost certainly _not_ writing code
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// just for the x86; if you assume x86 semantics, x86 hardware bugs and
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// implementations on other archtectures will cause your code to break. If you
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// do not know what you are doing, avoid these routines, and use a Mutex.
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//
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// It is incorrect to make direct assignments to/from an atomic variable.
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// You should use one of the Load or Store routines. The NoBarrier
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// versions are provided when no barriers are needed:
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// NoBarrier_Store()
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// NoBarrier_Load()
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// Although there are currently no compiler enforcement, you are encouraged
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// to use these.
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//
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#ifndef V8_ATOMICOPS_H_
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#define V8_ATOMICOPS_H_
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#include "../include/v8.h"
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#include "globals.h"
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namespace v8 {
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namespace internal {
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typedef int32_t Atomic32;
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#ifdef V8_HOST_ARCH_64_BIT
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// We need to be able to go between Atomic64 and AtomicWord implicitly. This
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// means Atomic64 and AtomicWord should be the same type on 64-bit.
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#if defined(__ILP32__) || defined(__APPLE__)
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// MacOS is an exception to the implicit conversion rule above,
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// because it uses long for intptr_t.
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typedef int64_t Atomic64;
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#else
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typedef intptr_t Atomic64;
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#endif
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#endif
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// Use AtomicWord for a machine-sized pointer. It will use the Atomic32 or
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// Atomic64 routines below, depending on your architecture.
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#if defined(__OpenBSD__) && defined(__i386__)
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typedef Atomic32 AtomicWord;
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#else
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typedef intptr_t AtomicWord;
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#endif
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// Atomically execute:
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// result = *ptr;
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// if (*ptr == old_value)
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// *ptr = new_value;
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// return result;
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//
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// I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value".
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// Always return the old value of "*ptr"
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//
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// This routine implies no memory barriers.
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Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value);
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// Atomically store new_value into *ptr, returning the previous value held in
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// *ptr. This routine implies no memory barriers.
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Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, Atomic32 new_value);
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// Atomically increment *ptr by "increment". Returns the new value of
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// *ptr with the increment applied. This routine implies no memory barriers.
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Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, Atomic32 increment);
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Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment);
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// These following lower-level operations are typically useful only to people
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// implementing higher-level synchronization operations like spinlocks,
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// mutexes, and condition-variables. They combine CompareAndSwap(), a load, or
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// a store with appropriate memory-ordering instructions. "Acquire" operations
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// ensure that no later memory access can be reordered ahead of the operation.
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// "Release" operations ensure that no previous memory access can be reordered
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// after the operation. "Barrier" operations have both "Acquire" and "Release"
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// semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory
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// access.
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Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value);
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Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value);
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void MemoryBarrier();
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void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value);
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void Acquire_Store(volatile Atomic32* ptr, Atomic32 value);
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void Release_Store(volatile Atomic32* ptr, Atomic32 value);
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Atomic32 NoBarrier_Load(volatile const Atomic32* ptr);
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Atomic32 Acquire_Load(volatile const Atomic32* ptr);
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Atomic32 Release_Load(volatile const Atomic32* ptr);
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// 64-bit atomic operations (only available on 64-bit processors).
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#ifdef V8_HOST_ARCH_64_BIT
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Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value);
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Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, Atomic64 new_value);
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Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment);
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Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment);
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Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value);
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Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value);
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void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value);
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void Acquire_Store(volatile Atomic64* ptr, Atomic64 value);
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void Release_Store(volatile Atomic64* ptr, Atomic64 value);
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Atomic64 NoBarrier_Load(volatile const Atomic64* ptr);
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Atomic64 Acquire_Load(volatile const Atomic64* ptr);
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Atomic64 Release_Load(volatile const Atomic64* ptr);
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#endif // V8_HOST_ARCH_64_BIT
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} } // namespace v8::internal
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// Include our platform specific implementation.
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#if defined(THREAD_SANITIZER)
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#include "atomicops_internals_tsan.h"
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#elif defined(_MSC_VER) && (V8_HOST_ARCH_IA32 || V8_HOST_ARCH_X64)
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#include "atomicops_internals_x86_msvc.h"
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#elif defined(__APPLE__) && (V8_HOST_ARCH_IA32 || V8_HOST_ARCH_X64)
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#include "atomicops_internals_x86_macosx.h"
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#elif defined(__GNUC__) && (V8_HOST_ARCH_IA32 || V8_HOST_ARCH_X64)
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#include "atomicops_internals_x86_gcc.h"
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#elif defined(__GNUC__) && V8_HOST_ARCH_ARM
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#include "atomicops_internals_arm_gcc.h"
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#elif defined(__GNUC__) && V8_HOST_ARCH_MIPS
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#include "atomicops_internals_mips_gcc.h"
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#else
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#error "Atomic operations are not supported on your platform"
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#endif
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#endif // V8_ATOMICOPS_H_
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