6b2a49ff83
instructions. The intention is that the snapshots generated by the simulator should be usable on the hardware. Instead of swi instructions we generate a branch to a swi instruction that is not part of the snapshot. The call/jump is patched up in the same way as other external references when the snapshot is deserialized. This only works for EABI targets: on old ABI targets we still emit some instructions not supported by the simulator (fp coprocessor instructions). Review URL: http://codereview.chromium.org/119036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2127 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
244 lines
8.6 KiB
C++
244 lines
8.6 KiB
C++
// Copyright 2009 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef V8_ARM_CONSTANTS_ARM_H_
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#define V8_ARM_CONSTANTS_ARM_H_
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// The simulator emulates the EABI so we define the USE_ARM_EABI macro if we
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// are not running on real ARM hardware. One reason for this is that the
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// old ABI uses fp registers in the calling convention and the simulator does
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// not simulate fp registers or coroutine instructions.
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#if defined(__ARM_EABI__) || !defined(__arm__)
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# define USE_ARM_EABI 1
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#endif
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namespace assembler {
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namespace arm {
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// Defines constants and accessor classes to assemble, disassemble and
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// simulate ARM instructions.
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//
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// Section references in the code refer to the "ARM Architecture Reference
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// Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
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//
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// Constants for specific fields are defined in their respective named enums.
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// General constants are in an anonymous enum in class Instr.
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typedef unsigned char byte;
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// Values for the condition field as defined in section A3.2
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enum Condition {
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no_condition = -1,
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EQ = 0, // equal
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NE = 1, // not equal
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CS = 2, // carry set/unsigned higher or same
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CC = 3, // carry clear/unsigned lower
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MI = 4, // minus/negative
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PL = 5, // plus/positive or zero
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VS = 6, // overflow
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VC = 7, // no overflow
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HI = 8, // unsigned higher
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LS = 9, // unsigned lower or same
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GE = 10, // signed greater than or equal
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LT = 11, // signed less than
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GT = 12, // signed greater than
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LE = 13, // signed less than or equal
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AL = 14, // always (unconditional)
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special_condition = 15, // special condition (refer to section A3.2.1)
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max_condition = 16
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};
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// Opcodes for Data-processing instructions (instructions with a type 0 and 1)
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// as defined in section A3.4
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enum Opcode {
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no_operand = -1,
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AND = 0, // Logical AND
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EOR = 1, // Logical Exclusive OR
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SUB = 2, // Subtract
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RSB = 3, // Reverse Subtract
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ADD = 4, // Add
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ADC = 5, // Add with Carry
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SBC = 6, // Subtract with Carry
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RSC = 7, // Reverse Subtract with Carry
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TST = 8, // Test
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TEQ = 9, // Test Equivalence
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CMP = 10, // Compare
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CMN = 11, // Compare Negated
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ORR = 12, // Logical (inclusive) OR
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MOV = 13, // Move
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BIC = 14, // Bit Clear
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MVN = 15, // Move Not
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max_operand = 16
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};
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// Shifter types for Data-processing operands as defined in section A5.1.2.
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enum Shift {
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no_shift = -1,
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LSL = 0, // Logical shift left
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LSR = 1, // Logical shift right
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ASR = 2, // Arithmetic shift right
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ROR = 3, // Rotate right
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max_shift = 4
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};
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// Special Software Interrupt codes when used in the presence of the ARM
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// simulator.
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enum SoftwareInterruptCodes {
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// transition to C code
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call_rt_redirected = 0x10,
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// break point
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break_point = 0x20
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};
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typedef int32_t instr_t;
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// The class Instr enables access to individual fields defined in the ARM
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// architecture instruction set encoding as described in figure A3-1.
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//
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// Example: Test whether the instruction at ptr does set the condition code
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// bits.
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//
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// bool InstructionSetsConditionCodes(byte* ptr) {
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// Instr* instr = Instr::At(ptr);
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// int type = instr->TypeField();
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// return ((type == 0) || (type == 1)) && instr->HasS();
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// }
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//
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class Instr {
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public:
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enum {
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kInstrSize = 4,
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kInstrSizeLog2 = 2,
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kPCReadOffset = 8
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};
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// Get the raw instruction bits.
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inline instr_t InstructionBits() const {
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return *reinterpret_cast<const instr_t*>(this);
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}
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// Set the raw instruction bits to value.
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inline void SetInstructionBits(instr_t value) {
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*reinterpret_cast<instr_t*>(this) = value;
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}
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// Read one particular bit out of the instruction bits.
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inline int Bit(int nr) const {
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return (InstructionBits() >> nr) & 1;
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}
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// Read a bit field out of the instruction bits.
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inline int Bits(int hi, int lo) const {
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return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
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}
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// Accessors for the different named fields used in the ARM encoding.
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// The naming of these accessor corresponds to figure A3-1.
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// Generally applicable fields
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inline Condition ConditionField() const {
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return static_cast<Condition>(Bits(31, 28));
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}
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inline int TypeField() const { return Bits(27, 25); }
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inline int RnField() const { return Bits(19, 16); }
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inline int RdField() const { return Bits(15, 12); }
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// Fields used in Data processing instructions
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inline Opcode OpcodeField() const {
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return static_cast<Opcode>(Bits(24, 21));
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}
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inline int SField() const { return Bit(20); }
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// with register
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inline int RmField() const { return Bits(3, 0); }
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inline Shift ShiftField() const { return static_cast<Shift>(Bits(6, 5)); }
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inline int RegShiftField() const { return Bit(4); }
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inline int RsField() const { return Bits(11, 8); }
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inline int ShiftAmountField() const { return Bits(11, 7); }
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// with immediate
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inline int RotateField() const { return Bits(11, 8); }
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inline int Immed8Field() const { return Bits(7, 0); }
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// Fields used in Load/Store instructions
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inline int PUField() const { return Bits(24, 23); }
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inline int BField() const { return Bit(22); }
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inline int WField() const { return Bit(21); }
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inline int LField() const { return Bit(20); }
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// with register uses same fields as Data processing instructions above
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// with immediate
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inline int Offset12Field() const { return Bits(11, 0); }
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// multiple
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inline int RlistField() const { return Bits(15, 0); }
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// extra loads and stores
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inline int SignField() const { return Bit(6); }
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inline int HField() const { return Bit(5); }
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inline int ImmedHField() const { return Bits(11, 8); }
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inline int ImmedLField() const { return Bits(3, 0); }
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// Fields used in Branch instructions
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inline int LinkField() const { return Bit(24); }
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inline int SImmed24Field() const { return ((InstructionBits() << 8) >> 8); }
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// Fields used in Software interrupt instructions
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inline SoftwareInterruptCodes SwiField() const {
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return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
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}
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// Test for special encodings of type 0 instructions (extra loads and stores,
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// as well as multiplications).
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inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); }
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// Special accessors that test for existence of a value.
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inline bool HasS() const { return SField() == 1; }
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inline bool HasB() const { return BField() == 1; }
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inline bool HasW() const { return WField() == 1; }
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inline bool HasL() const { return LField() == 1; }
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inline bool HasSign() const { return SignField() == 1; }
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inline bool HasH() const { return HField() == 1; }
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inline bool HasLink() const { return LinkField() == 1; }
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// Instructions are read of out a code stream. The only way to get a
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// reference to an instruction is to convert a pointer. There is no way
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// to allocate or create instances of class Instr.
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// Use the At(pc) function to create references to Instr.
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static Instr* At(byte* pc) { return reinterpret_cast<Instr*>(pc); }
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private:
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// We need to prevent the creation of instances of class Instr.
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DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
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};
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} } // namespace assembler::arm
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#endif // V8_ARM_CONSTANTS_ARM_H_
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