Lu Yahan 818d73ca18 [riscv64][register-alloc] Implement vector register independently allocating ... vector register has different register file from float register in Risc64 rvv extension. So this cl add third FPalising kind INDEPENDENT to allocate independently simd register. Bug: v8:11976 doc: https://docs.google.com/document/d/1UwmUwOI3eeIMYzZFRmeXmfyNXRFHNZAQ4BcN0ODdMmo/edit?usp=sharing Change-Id: I0fb8901294b4bc44b0bee55e630b60460e42bef2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3383513 Reviewed-by: Nico Hartmann <nicohartmann@chromium.org> Reviewed-by: Clemens Backes <clemensb@chromium.org> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79449}		2022-03-11 05:07:45 +00:00
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aligned-slot-allocator-unittest.cc	Reland "Reland "Reland "[compiler][wasm] Align Frame slots to value size"""	2021-03-05 19:49:19 +00:00
code-stub-assembler-unittest.cc	[Compiler] Remove untrusted code mitigations.	2021-08-12 12:58:24 +00:00
code-stub-assembler-unittest.h	Reland "[zone-compr] Introduce ZoneTypeTraits and ZoneCompression"	2020-07-31 11:43:08 +00:00
register-configuration-unittest.cc	[riscv64][register-alloc] Implement vector register independently allocating	2022-03-11 05:07:45 +00:00
source-position-table-unittest.cc	[backend] Fix source position annotations	2021-02-23 12:49:11 +00:00