75759805a9
The support for the old ABI is known to be broken and has been deprecated for some time now. Removed the instructions for loading and storing co-processor registers as they where only used to support the old ABI. R=karlklose@chromium.org BUG=v8:1316 TEST= Review URL: http://codereview.chromium.org//6822025 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7565 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
776 lines
26 KiB
C++
776 lines
26 KiB
C++
// Copyright 2011 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef V8_ARM_CONSTANTS_ARM_H_
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#define V8_ARM_CONSTANTS_ARM_H_
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// ARM EABI is required.
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#if defined(__arm__) && !defined(__ARM_EABI__)
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#error ARM EABI support is required.
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#endif
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// This means that interwork-compatible jump instructions are generated. We
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// want to generate them on the simulator too so it makes snapshots that can
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// be used on real hardware.
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#if defined(__THUMB_INTERWORK__) || !defined(__arm__)
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# define USE_THUMB_INTERWORK 1
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#endif
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#if defined(__ARM_ARCH_7A__) || \
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defined(__ARM_ARCH_7R__) || \
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defined(__ARM_ARCH_7__)
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# define CAN_USE_ARMV7_INSTRUCTIONS 1
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#endif
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#if defined(__ARM_ARCH_6__) || \
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defined(__ARM_ARCH_6J__) || \
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defined(__ARM_ARCH_6K__) || \
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defined(__ARM_ARCH_6Z__) || \
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defined(__ARM_ARCH_6ZK__) || \
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defined(__ARM_ARCH_6T2__) || \
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defined(CAN_USE_ARMV7_INSTRUCTIONS)
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# define CAN_USE_ARMV6_INSTRUCTIONS 1
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#endif
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#if defined(__ARM_ARCH_5T__) || \
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defined(__ARM_ARCH_5TE__) || \
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defined(CAN_USE_ARMV6_INSTRUCTIONS)
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# define CAN_USE_ARMV5_INSTRUCTIONS 1
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# define CAN_USE_THUMB_INSTRUCTIONS 1
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#endif
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// Simulator should support ARM5 instructions and unaligned access by default.
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#if !defined(__arm__)
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# define CAN_USE_ARMV5_INSTRUCTIONS 1
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# define CAN_USE_THUMB_INSTRUCTIONS 1
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# ifndef CAN_USE_UNALIGNED_ACCESSES
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# define CAN_USE_UNALIGNED_ACCESSES 1
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# endif
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#endif
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#if CAN_USE_UNALIGNED_ACCESSES
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#define V8_TARGET_CAN_READ_UNALIGNED 1
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#endif
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// Using blx may yield better code, so use it when required or when available
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#if defined(USE_THUMB_INTERWORK) || defined(CAN_USE_ARMV5_INSTRUCTIONS)
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#define USE_BLX 1
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#endif
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namespace v8 {
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namespace internal {
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// Constant pool marker.
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static const int kConstantPoolMarkerMask = 0xffe00000;
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static const int kConstantPoolMarker = 0x0c000000;
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static const int kConstantPoolLengthMask = 0x001ffff;
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// Number of registers in normal ARM mode.
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static const int kNumRegisters = 16;
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// VFP support.
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static const int kNumVFPSingleRegisters = 32;
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static const int kNumVFPDoubleRegisters = 16;
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static const int kNumVFPRegisters =
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kNumVFPSingleRegisters + kNumVFPDoubleRegisters;
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// PC is register 15.
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static const int kPCRegister = 15;
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static const int kNoRegister = -1;
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// -----------------------------------------------------------------------------
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// Conditions.
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// Defines constants and accessor classes to assemble, disassemble and
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// simulate ARM instructions.
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//
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// Section references in the code refer to the "ARM Architecture Reference
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// Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
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//
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// Constants for specific fields are defined in their respective named enums.
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// General constants are in an anonymous enum in class Instr.
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// Values for the condition field as defined in section A3.2
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enum Condition {
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kNoCondition = -1,
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eq = 0 << 28, // Z set Equal.
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ne = 1 << 28, // Z clear Not equal.
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cs = 2 << 28, // C set Unsigned higher or same.
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cc = 3 << 28, // C clear Unsigned lower.
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mi = 4 << 28, // N set Negative.
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pl = 5 << 28, // N clear Positive or zero.
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vs = 6 << 28, // V set Overflow.
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vc = 7 << 28, // V clear No overflow.
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hi = 8 << 28, // C set, Z clear Unsigned higher.
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ls = 9 << 28, // C clear or Z set Unsigned lower or same.
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ge = 10 << 28, // N == V Greater or equal.
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lt = 11 << 28, // N != V Less than.
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gt = 12 << 28, // Z clear, N == V Greater than.
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le = 13 << 28, // Z set or N != V Less then or equal
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al = 14 << 28, // Always.
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kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1).
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kNumberOfConditions = 16,
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// Aliases.
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hs = cs, // C set Unsigned higher or same.
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lo = cc // C clear Unsigned lower.
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};
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inline Condition NegateCondition(Condition cond) {
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ASSERT(cond != al);
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return static_cast<Condition>(cond ^ ne);
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}
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// Corresponds to transposing the operands of a comparison.
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inline Condition ReverseCondition(Condition cond) {
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switch (cond) {
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case lo:
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return hi;
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case hi:
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return lo;
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case hs:
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return ls;
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case ls:
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return hs;
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case lt:
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return gt;
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case gt:
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return lt;
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case ge:
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return le;
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case le:
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return ge;
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default:
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return cond;
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};
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}
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// -----------------------------------------------------------------------------
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// Instructions encoding.
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// Instr is merely used by the Assembler to distinguish 32bit integers
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// representing instructions from usual 32 bit values.
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// Instruction objects are pointers to 32bit values, and provide methods to
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// access the various ISA fields.
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typedef int32_t Instr;
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// Opcodes for Data-processing instructions (instructions with a type 0 and 1)
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// as defined in section A3.4
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enum Opcode {
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AND = 0 << 21, // Logical AND.
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EOR = 1 << 21, // Logical Exclusive OR.
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SUB = 2 << 21, // Subtract.
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RSB = 3 << 21, // Reverse Subtract.
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ADD = 4 << 21, // Add.
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ADC = 5 << 21, // Add with Carry.
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SBC = 6 << 21, // Subtract with Carry.
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RSC = 7 << 21, // Reverse Subtract with Carry.
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TST = 8 << 21, // Test.
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TEQ = 9 << 21, // Test Equivalence.
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CMP = 10 << 21, // Compare.
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CMN = 11 << 21, // Compare Negated.
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ORR = 12 << 21, // Logical (inclusive) OR.
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MOV = 13 << 21, // Move.
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BIC = 14 << 21, // Bit Clear.
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MVN = 15 << 21 // Move Not.
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};
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// The bits for bit 7-4 for some type 0 miscellaneous instructions.
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enum MiscInstructionsBits74 {
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// With bits 22-21 01.
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BX = 1 << 4,
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BXJ = 2 << 4,
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BLX = 3 << 4,
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BKPT = 7 << 4,
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// With bits 22-21 11.
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CLZ = 1 << 4
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};
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// Instruction encoding bits and masks.
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enum {
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H = 1 << 5, // Halfword (or byte).
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S6 = 1 << 6, // Signed (or unsigned).
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L = 1 << 20, // Load (or store).
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S = 1 << 20, // Set condition code (or leave unchanged).
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W = 1 << 21, // Writeback base register (or leave unchanged).
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A = 1 << 21, // Accumulate in multiply instruction (or not).
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B = 1 << 22, // Unsigned byte (or word).
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N = 1 << 22, // Long (or short).
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U = 1 << 23, // Positive (or negative) offset/index.
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P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing).
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I = 1 << 25, // Immediate shifter operand (or not).
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B4 = 1 << 4,
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B5 = 1 << 5,
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B6 = 1 << 6,
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B7 = 1 << 7,
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B8 = 1 << 8,
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B9 = 1 << 9,
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B12 = 1 << 12,
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B16 = 1 << 16,
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B18 = 1 << 18,
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B19 = 1 << 19,
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B20 = 1 << 20,
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B21 = 1 << 21,
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B22 = 1 << 22,
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B23 = 1 << 23,
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B24 = 1 << 24,
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B25 = 1 << 25,
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B26 = 1 << 26,
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B27 = 1 << 27,
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B28 = 1 << 28,
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// Instruction bit masks.
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kCondMask = 15 << 28,
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kALUMask = 0x6f << 21,
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kRdMask = 15 << 12, // In str instruction.
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kCoprocessorMask = 15 << 8,
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kOpCodeMask = 15 << 21, // In data-processing instructions.
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kImm24Mask = (1 << 24) - 1,
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kOff12Mask = (1 << 12) - 1
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};
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// -----------------------------------------------------------------------------
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// Addressing modes and instruction variants.
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// Condition code updating mode.
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enum SBit {
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SetCC = 1 << 20, // Set condition code.
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LeaveCC = 0 << 20 // Leave condition code unchanged.
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};
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// Status register selection.
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enum SRegister {
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CPSR = 0 << 22,
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SPSR = 1 << 22
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};
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// Shifter types for Data-processing operands as defined in section A5.1.2.
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enum ShiftOp {
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LSL = 0 << 5, // Logical shift left.
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LSR = 1 << 5, // Logical shift right.
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ASR = 2 << 5, // Arithmetic shift right.
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ROR = 3 << 5, // Rotate right.
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// RRX is encoded as ROR with shift_imm == 0.
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// Use a special code to make the distinction. The RRX ShiftOp is only used
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// as an argument, and will never actually be encoded. The Assembler will
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// detect it and emit the correct ROR shift operand with shift_imm == 0.
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RRX = -1,
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kNumberOfShifts = 4
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};
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// Status register fields.
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enum SRegisterField {
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CPSR_c = CPSR | 1 << 16,
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CPSR_x = CPSR | 1 << 17,
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CPSR_s = CPSR | 1 << 18,
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CPSR_f = CPSR | 1 << 19,
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SPSR_c = SPSR | 1 << 16,
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SPSR_x = SPSR | 1 << 17,
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SPSR_s = SPSR | 1 << 18,
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SPSR_f = SPSR | 1 << 19
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};
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// Status register field mask (or'ed SRegisterField enum values).
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typedef uint32_t SRegisterFieldMask;
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// Memory operand addressing mode.
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enum AddrMode {
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// Bit encoding P U W.
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Offset = (8|4|0) << 21, // Offset (without writeback to base).
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PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback.
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PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback.
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NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base).
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NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback.
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NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback.
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};
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// Load/store multiple addressing mode.
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enum BlockAddrMode {
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// Bit encoding P U W .
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da = (0|0|0) << 21, // Decrement after.
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ia = (0|4|0) << 21, // Increment after.
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db = (8|0|0) << 21, // Decrement before.
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ib = (8|4|0) << 21, // Increment before.
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da_w = (0|0|1) << 21, // Decrement after with writeback to base.
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ia_w = (0|4|1) << 21, // Increment after with writeback to base.
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db_w = (8|0|1) << 21, // Decrement before with writeback to base.
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ib_w = (8|4|1) << 21, // Increment before with writeback to base.
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// Alias modes for comparison when writeback does not matter.
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da_x = (0|0|0) << 21, // Decrement after.
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ia_x = (0|4|0) << 21, // Increment after.
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db_x = (8|0|0) << 21, // Decrement before.
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ib_x = (8|4|0) << 21, // Increment before.
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kBlockAddrModeMask = (8|4|1) << 21
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};
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// Coprocessor load/store operand size.
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enum LFlag {
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Long = 1 << 22, // Long load/store coprocessor.
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Short = 0 << 22 // Short load/store coprocessor.
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};
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// -----------------------------------------------------------------------------
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// Supervisor Call (svc) specific support.
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// Special Software Interrupt codes when used in the presence of the ARM
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// simulator.
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// svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
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// standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
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enum SoftwareInterruptCodes {
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// transition to C code
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kCallRtRedirected= 0x10,
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// break point
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kBreakpoint= 0x20,
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// stop
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kStopCode = 1 << 23
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};
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static const uint32_t kStopCodeMask = kStopCode - 1;
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static const uint32_t kMaxStopCode = kStopCode - 1;
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static const int32_t kDefaultStopCode = -1;
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// Type of VFP register. Determines register encoding.
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enum VFPRegPrecision {
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kSinglePrecision = 0,
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kDoublePrecision = 1
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};
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// VFP FPSCR constants.
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enum VFPConversionMode {
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kFPSCRRounding = 0,
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kDefaultRoundToZero = 1
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};
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// This mask does not include the "inexact" or "input denormal" cumulative
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// exceptions flags, because we usually don't want to check for it.
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static const uint32_t kVFPExceptionMask = 0xf;
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static const uint32_t kVFPInvalidOpExceptionBit = 1 << 0;
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static const uint32_t kVFPOverflowExceptionBit = 1 << 2;
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static const uint32_t kVFPUnderflowExceptionBit = 1 << 3;
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static const uint32_t kVFPInexactExceptionBit = 1 << 4;
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static const uint32_t kVFPFlushToZeroMask = 1 << 24;
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static const uint32_t kVFPNConditionFlagBit = 1 << 31;
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static const uint32_t kVFPZConditionFlagBit = 1 << 30;
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static const uint32_t kVFPCConditionFlagBit = 1 << 29;
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static const uint32_t kVFPVConditionFlagBit = 1 << 28;
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// VFP rounding modes. See ARM DDI 0406B Page A2-29.
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enum VFPRoundingMode {
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RN = 0 << 22, // Round to Nearest.
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RP = 1 << 22, // Round towards Plus Infinity.
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RM = 2 << 22, // Round towards Minus Infinity.
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RZ = 3 << 22, // Round towards zero.
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// Aliases.
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kRoundToNearest = RN,
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kRoundToPlusInf = RP,
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kRoundToMinusInf = RM,
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kRoundToZero = RZ
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};
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static const uint32_t kVFPRoundingModeMask = 3 << 22;
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enum CheckForInexactConversion {
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kCheckForInexactConversion,
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kDontCheckForInexactConversion
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};
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// -----------------------------------------------------------------------------
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// Hints.
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// Branch hints are not used on the ARM. They are defined so that they can
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// appear in shared function signatures, but will be ignored in ARM
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// implementations.
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enum Hint { no_hint };
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// Hints are not used on the arm. Negating is trivial.
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inline Hint NegateHint(Hint ignored) { return no_hint; }
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// -----------------------------------------------------------------------------
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// Specific instructions, constants, and masks.
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// These constants are declared in assembler-arm.cc, as they use named registers
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// and other constants.
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// add(sp, sp, 4) instruction (aka Pop())
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extern const Instr kPopInstruction;
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// str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r))
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// register r is not encoded.
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extern const Instr kPushRegPattern;
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// ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r))
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// register r is not encoded.
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extern const Instr kPopRegPattern;
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// mov lr, pc
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extern const Instr kMovLrPc;
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// ldr rd, [pc, #offset]
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extern const Instr kLdrPCMask;
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extern const Instr kLdrPCPattern;
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// blxcc rm
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extern const Instr kBlxRegMask;
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extern const Instr kBlxRegPattern;
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extern const Instr kMovMvnMask;
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extern const Instr kMovMvnPattern;
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extern const Instr kMovMvnFlip;
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extern const Instr kMovLeaveCCMask;
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extern const Instr kMovLeaveCCPattern;
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extern const Instr kMovwMask;
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extern const Instr kMovwPattern;
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extern const Instr kMovwLeaveCCFlip;
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extern const Instr kCmpCmnMask;
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extern const Instr kCmpCmnPattern;
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extern const Instr kCmpCmnFlip;
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extern const Instr kAddSubFlip;
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extern const Instr kAndBicFlip;
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// A mask for the Rd register for push, pop, ldr, str instructions.
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extern const Instr kLdrRegFpOffsetPattern;
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extern const Instr kStrRegFpOffsetPattern;
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extern const Instr kLdrRegFpNegOffsetPattern;
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extern const Instr kStrRegFpNegOffsetPattern;
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extern const Instr kLdrStrInstrTypeMask;
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extern const Instr kLdrStrInstrArgumentMask;
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extern const Instr kLdrStrOffsetMask;
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// -----------------------------------------------------------------------------
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// Instruction abstraction.
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// The class Instruction enables access to individual fields defined in the ARM
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// architecture instruction set encoding as described in figure A3-1.
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// Note that the Assembler uses typedef int32_t Instr.
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//
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// Example: Test whether the instruction at ptr does set the condition code
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// bits.
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//
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// bool InstructionSetsConditionCodes(byte* ptr) {
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// Instruction* instr = Instruction::At(ptr);
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// int type = instr->TypeValue();
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// return ((type == 0) || (type == 1)) && instr->HasS();
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// }
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//
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class Instruction {
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public:
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enum {
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kInstrSize = 4,
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kInstrSizeLog2 = 2,
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kPCReadOffset = 8
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};
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// Helper macro to define static accessors.
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// We use the cast to char* trick to bypass the strict anti-aliasing rules.
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#define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \
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static inline return_type Name(Instr instr) { \
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char* temp = reinterpret_cast<char*>(&instr); \
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return reinterpret_cast<Instruction*>(temp)->Name(); \
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}
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#define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name)
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// Get the raw instruction bits.
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inline Instr InstructionBits() const {
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return *reinterpret_cast<const Instr*>(this);
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}
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// Set the raw instruction bits to value.
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inline void SetInstructionBits(Instr value) {
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*reinterpret_cast<Instr*>(this) = value;
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}
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// Read one particular bit out of the instruction bits.
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inline int Bit(int nr) const {
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return (InstructionBits() >> nr) & 1;
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}
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// Read a bit field's value out of the instruction bits.
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inline int Bits(int hi, int lo) const {
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return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
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}
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// Read a bit field out of the instruction bits.
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inline int BitField(int hi, int lo) const {
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return InstructionBits() & (((2 << (hi - lo)) - 1) << lo);
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}
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// Static support.
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// Read one particular bit out of the instruction bits.
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static inline int Bit(Instr instr, int nr) {
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return (instr >> nr) & 1;
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}
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// Read the value of a bit field out of the instruction bits.
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static inline int Bits(Instr instr, int hi, int lo) {
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return (instr >> lo) & ((2 << (hi - lo)) - 1);
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}
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// Read a bit field out of the instruction bits.
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static inline int BitField(Instr instr, int hi, int lo) {
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return instr & (((2 << (hi - lo)) - 1) << lo);
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}
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// Accessors for the different named fields used in the ARM encoding.
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// The naming of these accessor corresponds to figure A3-1.
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//
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// Two kind of accessors are declared:
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// - <Name>Field() will return the raw field, ie the field's bits at their
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// original place in the instruction encoding.
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// eg. if instr is the 'addgt r0, r1, r2' instruction, encoded as 0xC0810002
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// ConditionField(instr) will return 0xC0000000.
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// - <Name>Value() will return the field value, shifted back to bit 0.
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// eg. if instr is the 'addgt r0, r1, r2' instruction, encoded as 0xC0810002
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// ConditionField(instr) will return 0xC.
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// Generally applicable fields
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inline Condition ConditionValue() const {
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return static_cast<Condition>(Bits(31, 28));
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}
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inline Condition ConditionField() const {
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return static_cast<Condition>(BitField(31, 28));
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}
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DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue);
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DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField);
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inline int TypeValue() const { return Bits(27, 25); }
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inline int RnValue() const { return Bits(19, 16); }
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DECLARE_STATIC_ACCESSOR(RnValue);
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inline int RdValue() const { return Bits(15, 12); }
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DECLARE_STATIC_ACCESSOR(RdValue);
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inline int CoprocessorValue() const { return Bits(11, 8); }
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// Support for VFP.
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// Vn(19-16) | Vd(15-12) | Vm(3-0)
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inline int VnValue() const { return Bits(19, 16); }
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inline int VmValue() const { return Bits(3, 0); }
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inline int VdValue() const { return Bits(15, 12); }
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inline int NValue() const { return Bit(7); }
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inline int MValue() const { return Bit(5); }
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inline int DValue() const { return Bit(22); }
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inline int RtValue() const { return Bits(15, 12); }
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inline int PValue() const { return Bit(24); }
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inline int UValue() const { return Bit(23); }
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inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); }
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inline int Opc2Value() const { return Bits(19, 16); }
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inline int Opc3Value() const { return Bits(7, 6); }
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inline int SzValue() const { return Bit(8); }
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inline int VLValue() const { return Bit(20); }
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inline int VCValue() const { return Bit(8); }
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inline int VAValue() const { return Bits(23, 21); }
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inline int VBValue() const { return Bits(6, 5); }
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inline int VFPNRegValue(VFPRegPrecision pre) {
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return VFPGlueRegValue(pre, 16, 7);
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}
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inline int VFPMRegValue(VFPRegPrecision pre) {
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return VFPGlueRegValue(pre, 0, 5);
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}
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inline int VFPDRegValue(VFPRegPrecision pre) {
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return VFPGlueRegValue(pre, 12, 22);
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}
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// Fields used in Data processing instructions
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inline int OpcodeValue() const {
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return static_cast<Opcode>(Bits(24, 21));
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}
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inline Opcode OpcodeField() const {
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return static_cast<Opcode>(BitField(24, 21));
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}
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inline int SValue() const { return Bit(20); }
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// with register
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inline int RmValue() const { return Bits(3, 0); }
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DECLARE_STATIC_ACCESSOR(RmValue);
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inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
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inline ShiftOp ShiftField() const {
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return static_cast<ShiftOp>(BitField(6, 5));
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}
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inline int RegShiftValue() const { return Bit(4); }
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inline int RsValue() const { return Bits(11, 8); }
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inline int ShiftAmountValue() const { return Bits(11, 7); }
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// with immediate
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inline int RotateValue() const { return Bits(11, 8); }
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inline int Immed8Value() const { return Bits(7, 0); }
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inline int Immed4Value() const { return Bits(19, 16); }
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inline int ImmedMovwMovtValue() const {
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return Immed4Value() << 12 | Offset12Value(); }
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// Fields used in Load/Store instructions
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inline int PUValue() const { return Bits(24, 23); }
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inline int PUField() const { return BitField(24, 23); }
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inline int BValue() const { return Bit(22); }
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inline int WValue() const { return Bit(21); }
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inline int LValue() const { return Bit(20); }
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// with register uses same fields as Data processing instructions above
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// with immediate
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inline int Offset12Value() const { return Bits(11, 0); }
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// multiple
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inline int RlistValue() const { return Bits(15, 0); }
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// extra loads and stores
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inline int SignValue() const { return Bit(6); }
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inline int HValue() const { return Bit(5); }
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inline int ImmedHValue() const { return Bits(11, 8); }
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inline int ImmedLValue() const { return Bits(3, 0); }
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// Fields used in Branch instructions
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inline int LinkValue() const { return Bit(24); }
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inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); }
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// Fields used in Software interrupt instructions
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inline SoftwareInterruptCodes SvcValue() const {
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return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
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}
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// Test for special encodings of type 0 instructions (extra loads and stores,
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// as well as multiplications).
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inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); }
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// Test for miscellaneous instructions encodings of type 0 instructions.
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inline bool IsMiscType0() const { return (Bit(24) == 1)
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&& (Bit(23) == 0)
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&& (Bit(20) == 0)
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&& ((Bit(7) == 0)); }
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// Test for a stop instruction.
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inline bool IsStop() const {
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return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode);
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}
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// Special accessors that test for existence of a value.
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inline bool HasS() const { return SValue() == 1; }
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inline bool HasB() const { return BValue() == 1; }
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inline bool HasW() const { return WValue() == 1; }
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inline bool HasL() const { return LValue() == 1; }
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inline bool HasU() const { return UValue() == 1; }
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inline bool HasSign() const { return SignValue() == 1; }
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inline bool HasH() const { return HValue() == 1; }
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inline bool HasLink() const { return LinkValue() == 1; }
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// Decoding the double immediate in the vmov instruction.
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double DoubleImmedVmov() const;
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// Instructions are read of out a code stream. The only way to get a
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// reference to an instruction is to convert a pointer. There is no way
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// to allocate or create instances of class Instruction.
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// Use the At(pc) function to create references to Instruction.
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static Instruction* At(byte* pc) {
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return reinterpret_cast<Instruction*>(pc);
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}
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private:
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// Join split register codes, depending on single or double precision.
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// four_bit is the position of the least-significant bit of the four
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// bit specifier. one_bit is the position of the additional single bit
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// specifier.
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inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) {
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if (pre == kSinglePrecision) {
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return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
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}
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return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
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}
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// We need to prevent the creation of instances of class Instruction.
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DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
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};
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// Helper functions for converting between register numbers and names.
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class Registers {
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public:
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// Return the name of the register.
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static const char* Name(int reg);
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// Lookup the register number for the name provided.
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static int Number(const char* name);
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struct RegisterAlias {
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int reg;
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const char* name;
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};
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private:
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static const char* names_[kNumRegisters];
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static const RegisterAlias aliases_[];
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};
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// Helper functions for converting between VFP register numbers and names.
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class VFPRegisters {
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public:
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// Return the name of the register.
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static const char* Name(int reg, bool is_double);
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// Lookup the register number for the name provided.
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// Set flag pointed by is_double to true if register
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// is double-precision.
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static int Number(const char* name, bool* is_double);
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private:
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static const char* names_[kNumVFPRegisters];
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};
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} } // namespace v8::internal
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#endif // V8_ARM_CONSTANTS_ARM_H_
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