d4b533d41b
R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/259183002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21035 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
86 lines
2.6 KiB
C++
86 lines
2.6 KiB
C++
// Copyright 2006-2009 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// CPU specific code for arm independent of OS goes here.
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#ifdef __arm__
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#ifdef __QNXNTO__
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#include <sys/mman.h> // for cache flushing.
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#undef MAP_TYPE
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#else
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#include <sys/syscall.h> // for cache flushing.
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#endif
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#endif
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#include "v8.h"
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#if V8_TARGET_ARCH_ARM
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#include "cpu.h"
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#include "macro-assembler.h"
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#include "simulator.h" // for cache flushing.
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namespace v8 {
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namespace internal {
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void CPU::FlushICache(void* start, size_t size) {
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// Nothing to do flushing no instructions.
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if (size == 0) {
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return;
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}
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#if defined(USE_SIMULATOR)
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// Not generating ARM instructions for C-code. This means that we are
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// building an ARM emulator based target. We should notify the simulator
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// that the Icache was flushed.
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// None of this code ends up in the snapshot so there are no issues
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// around whether or not to generate the code when building snapshots.
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Simulator::FlushICache(Isolate::Current()->simulator_i_cache(), start, size);
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#elif V8_OS_QNX
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msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE);
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#else
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// Ideally, we would call
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// syscall(__ARM_NR_cacheflush, start,
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// reinterpret_cast<intptr_t>(start) + size, 0);
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// however, syscall(int, ...) is not supported on all platforms, especially
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// not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.
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register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
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register uint32_t end asm("a2") =
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reinterpret_cast<uint32_t>(start) + size;
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register uint32_t flg asm("a3") = 0;
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#if defined (__arm__) && !defined(__thumb__)
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// __arm__ may be defined in thumb mode.
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register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
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asm volatile(
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"svc 0x0"
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: "=r" (beg)
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: "0" (beg), "r" (end), "r" (flg), "r" (scno));
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#else
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// r7 is reserved by the EABI in thumb mode.
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asm volatile(
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"@ Enter ARM Mode \n\t"
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"adr r3, 1f \n\t"
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"bx r3 \n\t"
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".ALIGN 4 \n\t"
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".ARM \n"
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"1: push {r7} \n\t"
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"mov r7, %4 \n\t"
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"svc 0x0 \n\t"
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"pop {r7} \n\t"
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"@ Enter THUMB Mode\n\t"
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"adr r3, 2f+1 \n\t"
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"bx r3 \n\t"
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".THUMB \n"
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"2: \n\t"
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: "=r" (beg)
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: "0" (beg), "r" (end), "r" (flg), "r" (__ARM_NR_cacheflush)
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: "r3");
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#endif
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#endif
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}
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} } // namespace v8::internal
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#endif // V8_TARGET_ARCH_ARM
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