942a67ca01
This is a reland of commit 491de34bcc
co-authors: Ji Qiu <qiuji@iscas.ac.cn>
Alvise De Faveri Tron <elvisilde@gmail.com>
Usman Zain <uszain@gmail.com>
Zheng Quan <vitalyankh@gmail.com>
Original change's description:
> [riscv32] Add RISCV32 backend
>
> This very large changeset adds support for RISCV32.
>
> Bug: v8:13025
> Change-Id: Ieacc857131e6620f0fcfd7daa88a0f8d77056aa9
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3736732
> Reviewed-by: Michael Achenbach <machenbach@chromium.org>
> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
> Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
> Reviewed-by: Andreas Haas <ahaas@chromium.org>
> Reviewed-by: Hannes Payer <hpayer@chromium.org>
> Reviewed-by: Nico Hartmann <nicohartmann@chromium.org>
> Cr-Commit-Position: refs/heads/main@{#82053}
Bug: v8:13025
Change-Id: I220fae4b8e2679bdc111724e08817b079b373bd5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3807124
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Reviewed-by: Hannes Payer <hpayer@chromium.org>
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Cr-Commit-Position: refs/heads/main@{#82198}
154 lines
5.2 KiB
Python
154 lines
5.2 KiB
Python
# Copyright 2022 the V8 project authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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from testrunner.local import utils
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# Increase the timeout for these:
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SLOW_ARCHS = [
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"arm", "arm64", "mips", "mipsel", "mips64", "mips64el", "s390", "s390x",
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"riscv32", "riscv64", "loong64"
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]
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class BuildConfig(object):
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def __init__(self, build_config, options):
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self.options = options
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# In V8 land, GN's x86 is called ia32.
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if build_config['v8_target_cpu'] == 'x86':
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self.arch = 'ia32'
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else:
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self.arch = build_config['v8_target_cpu']
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self.asan = build_config['is_asan']
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self.cfi_vptr = build_config['is_cfi']
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self.control_flow_integrity = build_config['v8_control_flow_integrity']
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self.concurrent_marking = build_config['v8_enable_concurrent_marking']
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self.single_generation = build_config['v8_enable_single_generation']
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self.dcheck_always_on = build_config['dcheck_always_on']
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self.gcov_coverage = build_config['is_gcov_coverage']
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self.is_android = build_config['is_android']
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self.is_clang = build_config['is_clang']
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self.is_debug = build_config['is_debug']
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self.is_full_debug = build_config['is_full_debug']
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self.msan = build_config['is_msan']
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self.no_i18n = not build_config['v8_enable_i18n_support']
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self.predictable = build_config['v8_enable_verify_predictable']
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self.simulator_run = (
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build_config['target_cpu'] != build_config['v8_target_cpu'])
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self.tsan = build_config['is_tsan']
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# TODO(machenbach): We only have ubsan not ubsan_vptr.
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self.ubsan_vptr = build_config['is_ubsan_vptr']
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self.verify_csa = build_config['v8_enable_verify_csa']
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self.lite_mode = build_config['v8_enable_lite_mode']
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self.pointer_compression = build_config['v8_enable_pointer_compression']
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self.pointer_compression_shared_cage = build_config[
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'v8_enable_pointer_compression_shared_cage']
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self.shared_ro_heap = build_config['v8_enable_shared_ro_heap']
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self.sandbox = build_config['v8_enable_sandbox']
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self.third_party_heap = build_config['v8_enable_third_party_heap']
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self.webassembly = build_config['v8_enable_webassembly']
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self.dict_property_const_tracking = build_config[
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'v8_dict_property_const_tracking']
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# Export only for MIPS target
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if self.arch in ['mips', 'mipsel', 'mips64', 'mips64el']:
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self._mips_arch_variant = build_config['mips_arch_variant']
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self.mips_use_msa = build_config['mips_use_msa']
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@property
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def use_sanitizer(self):
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return (self.asan or self.cfi_vptr or self.msan or self.tsan or
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self.ubsan_vptr)
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@property
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def no_js_shared_memory(self):
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return (not self.shared_ro_heap) or (
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self.pointer_compression and not self.pointer_compression_shared_cage)
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@property
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def is_mips_arch(self):
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return self.arch in ['mipsel', 'mips', 'mips64', 'mips64el']
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@property
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def simd_mips(self):
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return (self.is_mips_arch and self._mips_arch_variant == "r6" and
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self.mips_use_msa)
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@property
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def mips_arch_variant(self):
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return (self.is_mips_arch and self._mips_arch_variant)
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@property
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def no_simd_hardware(self):
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# TODO(liviurau): Add some tests and refactor the logic here.
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# We try to find all the reasons why we have no_simd.
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no_simd_hardware = any(i in self.options.extra_flags for i in [
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'--noenable-sse3', '--no-enable-sse3', '--noenable-ssse3',
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'--no-enable-ssse3', '--noenable-sse4-1', '--no-enable-sse4_1'
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])
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# Set no_simd_hardware on architectures without Simd enabled.
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if self.arch == 'mips64el' or \
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self.arch == 'mipsel':
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no_simd_hardware = not self.simd_mips
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if self.arch == 'loong64' or \
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self.arch == 'riscv32':
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no_simd_hardware = True
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# S390 hosts without VEF1 do not support Simd.
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if self.arch == 's390x' and \
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not self.simulator_run and \
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not utils.IsS390SimdSupported():
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no_simd_hardware = True
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# Ppc64 processors earlier than POWER9 do not support Simd instructions
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if self.arch == 'ppc64' and \
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not self.simulator_run and \
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utils.GuessPowerProcessorVersion() < 9:
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no_simd_hardware = True
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return no_simd_hardware
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def timeout_scalefactor(self, initial_factor):
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"""Increases timeout for slow build configurations."""
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factors = dict(
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lite_mode=2,
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predictable=4,
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tsan=2,
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use_sanitizer=1.5,
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is_full_debug=4,
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)
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result = initial_factor
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for k, v in factors.items():
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if getattr(self, k, False):
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result *= v
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if self.arch in SLOW_ARCHS:
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result *= 4.5
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return result
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def __str__(self):
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attrs = [
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'asan',
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'cfi_vptr',
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'control_flow_integrity',
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'dcheck_always_on',
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'gcov_coverage',
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'msan',
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'no_i18n',
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'predictable',
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'tsan',
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'ubsan_vptr',
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'verify_csa',
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'lite_mode',
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'pointer_compression',
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'pointer_compression_shared_cage',
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'sandbox',
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'third_party_heap',
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'webassembly',
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'dict_property_const_tracking',
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]
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detected_options = [attr for attr in attrs if getattr(self, attr, False)]
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return '\n'.join(detected_options)
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