3b2470d296
Mainly, there were errors concerning blank lines before and after class access control sections [whitespace/blank_line]. BEFORE an access control section (e.g. public:, private:) there should be a blank line (except for the section right after the class declaration). AFTER an access control section there should be no blank line. TBR=ager@chromium.org git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8193 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
1143 lines
38 KiB
C++
1143 lines
38 KiB
C++
// Copyright (c) 1994-2006 Sun Microsystems Inc.
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// All Rights Reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// - Redistribution in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// - Neither the name of Sun Microsystems or the names of contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The original source code covered by the above license above has been
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// modified significantly by Google Inc.
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// Copyright 2011 the V8 project authors. All rights reserved.
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#ifndef V8_MIPS_ASSEMBLER_MIPS_H_
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#define V8_MIPS_ASSEMBLER_MIPS_H_
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#include <stdio.h>
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#include "assembler.h"
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#include "constants-mips.h"
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#include "serialize.h"
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namespace v8 {
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namespace internal {
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// CPU Registers.
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//
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// 1) We would prefer to use an enum, but enum values are assignment-
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// compatible with int, which has caused code-generation bugs.
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//
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// 2) We would prefer to use a class instead of a struct but we don't like
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// the register initialization to depend on the particular initialization
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// order (which appears to be different on OS X, Linux, and Windows for the
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// installed versions of C++ we tried). Using a struct permits C-style
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// "initialization". Also, the Register objects cannot be const as this
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// forces initialization stubs in MSVC, making us dependent on initialization
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// order.
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//
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// 3) By not using an enum, we are possibly preventing the compiler from
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// doing certain constant folds, which may significantly reduce the
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// code generated for some assembly instructions (because they boil down
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// to a few constants). If this is a problem, we could change the code
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// such that we use an enum in optimized mode, and the struct in debug
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// mode. This way we get the compile-time error checking in debug mode
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// and best performance in optimized code.
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// -----------------------------------------------------------------------------
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// Implementation of Register and FPURegister.
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// Core register.
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struct Register {
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static const int kNumRegisters = v8::internal::kNumRegisters;
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static const int kNumAllocatableRegisters = 14; // v0 through t7.
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static const int kSizeInBytes = 4;
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static int ToAllocationIndex(Register reg) {
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return reg.code() - 2; // zero_reg and 'at' are skipped.
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}
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static Register FromAllocationIndex(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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return from_code(index + 2); // zero_reg and 'at' are skipped.
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}
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static const char* AllocationIndexToString(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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const char* const names[] = {
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"v0",
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"v1",
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"a0",
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"a1",
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"a2",
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"a3",
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"t0",
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"t1",
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"t2",
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"t3",
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"t4",
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"t5",
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"t6",
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"t7",
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};
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return names[index];
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}
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static Register from_code(int code) {
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Register r = { code };
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return r;
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}
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bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
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bool is(Register reg) const { return code_ == reg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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// Unfortunately we can't make this private in a struct.
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int code_;
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};
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const Register no_reg = { -1 };
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const Register zero_reg = { 0 };
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const Register at = { 1 };
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const Register v0 = { 2 };
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const Register v1 = { 3 };
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const Register a0 = { 4 };
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const Register a1 = { 5 };
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const Register a2 = { 6 };
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const Register a3 = { 7 };
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const Register t0 = { 8 };
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const Register t1 = { 9 };
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const Register t2 = { 10 };
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const Register t3 = { 11 };
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const Register t4 = { 12 };
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const Register t5 = { 13 };
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const Register t6 = { 14 };
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const Register t7 = { 15 };
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const Register s0 = { 16 };
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const Register s1 = { 17 };
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const Register s2 = { 18 };
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const Register s3 = { 19 };
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const Register s4 = { 20 };
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const Register s5 = { 21 };
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const Register s6 = { 22 };
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const Register s7 = { 23 };
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const Register t8 = { 24 };
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const Register t9 = { 25 };
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const Register k0 = { 26 };
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const Register k1 = { 27 };
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const Register gp = { 28 };
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const Register sp = { 29 };
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const Register s8_fp = { 30 };
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const Register ra = { 31 };
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int ToNumber(Register reg);
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Register ToRegister(int num);
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// Coprocessor register.
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struct FPURegister {
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static const int kNumRegisters = v8::internal::kNumFPURegisters;
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// f0 has been excluded from allocation. This is following ia32
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// where xmm0 is excluded.
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static const int kNumAllocatableRegisters = 15;
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static int ToAllocationIndex(FPURegister reg) {
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ASSERT(reg.code() != 0);
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ASSERT(reg.code() % 2 == 0);
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return (reg.code() / 2) - 1;
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}
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static FPURegister FromAllocationIndex(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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return from_code((index + 1) * 2);
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}
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static const char* AllocationIndexToString(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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const char* const names[] = {
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"f2",
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"f4",
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"f6",
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"f8",
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"f10",
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"f12",
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"f14",
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"f16",
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"f18",
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"f20",
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"f22",
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"f24",
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"f26",
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"f28",
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"f30"
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};
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return names[index];
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}
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static FPURegister from_code(int code) {
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FPURegister r = { code };
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return r;
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}
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bool is_valid() const { return 0 <= code_ && code_ < kNumFPURegisters ; }
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bool is(FPURegister creg) const { return code_ == creg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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void setcode(int f) {
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code_ = f;
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ASSERT(is_valid());
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}
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// Unfortunately we can't make this private in a struct.
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int code_;
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};
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typedef FPURegister DoubleRegister;
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const FPURegister no_creg = { -1 };
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const FPURegister f0 = { 0 }; // Return value in hard float mode.
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const FPURegister f1 = { 1 };
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const FPURegister f2 = { 2 };
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const FPURegister f3 = { 3 };
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const FPURegister f4 = { 4 };
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const FPURegister f5 = { 5 };
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const FPURegister f6 = { 6 };
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const FPURegister f7 = { 7 };
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const FPURegister f8 = { 8 };
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const FPURegister f9 = { 9 };
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const FPURegister f10 = { 10 };
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const FPURegister f11 = { 11 };
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const FPURegister f12 = { 12 }; // Arg 0 in hard float mode.
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const FPURegister f13 = { 13 };
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const FPURegister f14 = { 14 }; // Arg 1 in hard float mode.
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const FPURegister f15 = { 15 };
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const FPURegister f16 = { 16 };
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const FPURegister f17 = { 17 };
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const FPURegister f18 = { 18 };
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const FPURegister f19 = { 19 };
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const FPURegister f20 = { 20 };
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const FPURegister f21 = { 21 };
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const FPURegister f22 = { 22 };
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const FPURegister f23 = { 23 };
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const FPURegister f24 = { 24 };
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const FPURegister f25 = { 25 };
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const FPURegister f26 = { 26 };
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const FPURegister f27 = { 27 };
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const FPURegister f28 = { 28 };
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const FPURegister f29 = { 29 };
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const FPURegister f30 = { 30 };
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const FPURegister f31 = { 31 };
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// FPU (coprocessor 1) control registers.
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// Currently only FCSR (#31) is implemented.
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struct FPUControlRegister {
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bool is_valid() const { return code_ == kFCSRRegister; }
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bool is(FPUControlRegister creg) const { return code_ == creg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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void setcode(int f) {
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code_ = f;
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ASSERT(is_valid());
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}
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// Unfortunately we can't make this private in a struct.
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int code_;
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};
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const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister };
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const FPUControlRegister FCSR = { kFCSRRegister };
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// -----------------------------------------------------------------------------
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// Machine instruction Operands.
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// Class Operand represents a shifter operand in data processing instructions.
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class Operand BASE_EMBEDDED {
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public:
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// Immediate.
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INLINE(explicit Operand(int32_t immediate,
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RelocInfo::Mode rmode = RelocInfo::NONE));
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INLINE(explicit Operand(const ExternalReference& f));
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INLINE(explicit Operand(const char* s));
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INLINE(explicit Operand(Object** opp));
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INLINE(explicit Operand(Context** cpp));
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explicit Operand(Handle<Object> handle);
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INLINE(explicit Operand(Smi* value));
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// Register.
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INLINE(explicit Operand(Register rm));
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// Return true if this is a register operand.
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INLINE(bool is_reg() const);
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Register rm() const { return rm_; }
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private:
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Register rm_;
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int32_t imm32_; // Valid if rm_ == no_reg.
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RelocInfo::Mode rmode_;
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friend class Assembler;
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friend class MacroAssembler;
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};
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// On MIPS we have only one adressing mode with base_reg + offset.
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// Class MemOperand represents a memory operand in load and store instructions.
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class MemOperand : public Operand {
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public:
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explicit MemOperand(Register rn, int32_t offset = 0);
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private:
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int32_t offset_;
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friend class Assembler;
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};
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// CpuFeatures keeps track of which features are supported by the target CPU.
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// Supported features must be enabled by a Scope before use.
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class CpuFeatures : public AllStatic {
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public:
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// Detect features of the target CPU. Set safe defaults if the serializer
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// is enabled (snapshots must be portable).
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static void Probe();
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// Check whether a feature is supported by the target CPU.
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static bool IsSupported(CpuFeature f) {
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ASSERT(initialized_);
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if (f == FPU && !FLAG_enable_fpu) return false;
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return (supported_ & (1u << f)) != 0;
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}
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#ifdef DEBUG
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// Check whether a feature is currently enabled.
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static bool IsEnabled(CpuFeature f) {
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ASSERT(initialized_);
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Isolate* isolate = Isolate::UncheckedCurrent();
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if (isolate == NULL) {
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// When no isolate is available, work as if we're running in
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// release mode.
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return IsSupported(f);
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}
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unsigned enabled = static_cast<unsigned>(isolate->enabled_cpu_features());
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return (enabled & (1u << f)) != 0;
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}
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#endif
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// Enable a specified feature within a scope.
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class Scope BASE_EMBEDDED {
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#ifdef DEBUG
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public:
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explicit Scope(CpuFeature f) {
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unsigned mask = 1u << f;
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ASSERT(CpuFeatures::IsSupported(f));
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ASSERT(!Serializer::enabled() ||
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(CpuFeatures::found_by_runtime_probing_ & mask) == 0);
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isolate_ = Isolate::UncheckedCurrent();
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old_enabled_ = 0;
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if (isolate_ != NULL) {
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old_enabled_ = static_cast<unsigned>(isolate_->enabled_cpu_features());
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isolate_->set_enabled_cpu_features(old_enabled_ | mask);
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}
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}
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~Scope() {
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ASSERT_EQ(Isolate::UncheckedCurrent(), isolate_);
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if (isolate_ != NULL) {
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isolate_->set_enabled_cpu_features(old_enabled_);
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}
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}
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private:
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Isolate* isolate_;
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unsigned old_enabled_;
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#else
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public:
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explicit Scope(CpuFeature f) {}
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#endif
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};
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class TryForceFeatureScope BASE_EMBEDDED {
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public:
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explicit TryForceFeatureScope(CpuFeature f)
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: old_supported_(CpuFeatures::supported_) {
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if (CanForce()) {
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CpuFeatures::supported_ |= (1u << f);
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}
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}
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~TryForceFeatureScope() {
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if (CanForce()) {
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CpuFeatures::supported_ = old_supported_;
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}
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}
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private:
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static bool CanForce() {
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// It's only safe to temporarily force support of CPU features
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// when there's only a single isolate, which is guaranteed when
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// the serializer is enabled.
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return Serializer::enabled();
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}
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const unsigned old_supported_;
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};
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private:
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#ifdef DEBUG
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static bool initialized_;
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#endif
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static unsigned supported_;
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static unsigned found_by_runtime_probing_;
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DISALLOW_COPY_AND_ASSIGN(CpuFeatures);
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};
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class Assembler : public AssemblerBase {
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public:
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// Create an assembler. Instructions and relocation information are emitted
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// into a buffer, with the instructions starting from the beginning and the
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// relocation information starting from the end of the buffer. See CodeDesc
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// for a detailed comment on the layout (globals.h).
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//
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// If the provided buffer is NULL, the assembler allocates and grows its own
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// buffer, and buffer_size determines the initial buffer size. The buffer is
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// owned by the assembler and deallocated upon destruction of the assembler.
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//
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// If the provided buffer is not NULL, the assembler uses the provided buffer
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// for code generation and assumes its size to be buffer_size. If the buffer
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// is too small, a fatal error occurs. No deallocation of the buffer is done
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// upon destruction of the assembler.
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Assembler(Isolate* isolate, void* buffer, int buffer_size);
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~Assembler();
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// Overrides the default provided by FLAG_debug_code.
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void set_emit_debug_code(bool value) { emit_debug_code_ = value; }
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// GetCode emits any pending (non-emitted) code and fills the descriptor
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// desc. GetCode() is idempotent; it returns the same result if no other
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// Assembler functions are invoked in between GetCode() calls.
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void GetCode(CodeDesc* desc);
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// Label operations & relative jumps (PPUM Appendix D).
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//
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// Takes a branch opcode (cc) and a label (L) and generates
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// either a backward branch or a forward branch and links it
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// to the label fixup chain. Usage:
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//
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// Label L; // unbound label
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// j(cc, &L); // forward branch to unbound label
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// bind(&L); // bind label to the current pc
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// j(cc, &L); // backward branch to bound label
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// bind(&L); // illegal: a label may be bound only once
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//
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// Note: The same Label can be used for forward and backward branches
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// but it may be bound only once.
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void bind(Label* L); // Binds an unbound label L to current code position.
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// Returns the branch offset to the given label from the current code
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// position. Links the label to the current position if it is still unbound.
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// Manages the jump elimination optimization if the second parameter is true.
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int32_t branch_offset(Label* L, bool jump_elimination_allowed);
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int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
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int32_t o = branch_offset(L, jump_elimination_allowed);
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ASSERT((o & 3) == 0); // Assert the offset is aligned.
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return o >> 2;
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}
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// Puts a labels target address at the given position.
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// The high 8 bits are set to zero.
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void label_at_put(Label* L, int at_offset);
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// Read/Modify the code target address in the branch/call instruction at pc.
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static Address target_address_at(Address pc);
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static void set_target_address_at(Address pc, Address target);
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// This sets the branch destination (which gets loaded at the call address).
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// This is for calls and branches within generated code.
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inline static void set_target_at(Address instruction_payload,
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Address target) {
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set_target_address_at(instruction_payload, target);
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}
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// This sets the branch destination.
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// This is for calls and branches to runtime code.
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inline static void set_external_target_at(Address instruction_payload,
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Address target) {
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set_target_address_at(instruction_payload, target);
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}
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// Size of an instruction.
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static const int kInstrSize = sizeof(Instr);
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|
|
// Difference between address of current opcode and target address offset.
|
|
static const int kBranchPCOffset = 4;
|
|
|
|
// Here we are patching the address in the LUI/ORI instruction pair.
|
|
// These values are used in the serialization process and must be zero for
|
|
// MIPS platform, as Code, Embedded Object or External-reference pointers
|
|
// are split across two consecutive instructions and don't exist separately
|
|
// in the code, so the serializer should not step forwards in memory after
|
|
// a target is resolved and written.
|
|
static const int kCallTargetSize = 0 * kInstrSize;
|
|
static const int kExternalTargetSize = 0 * kInstrSize;
|
|
|
|
// Number of consecutive instructions used to store 32bit constant.
|
|
// Used in RelocInfo::target_address_address() function to tell serializer
|
|
// address of the instruction that follows LUI/ORI instruction pair.
|
|
static const int kInstructionsFor32BitConstant = 2;
|
|
|
|
// Distance between the instruction referring to the address of the call
|
|
// target and the return address.
|
|
static const int kCallTargetAddressOffset = 4 * kInstrSize;
|
|
|
|
// Distance between start of patched return sequence and the emitted address
|
|
// to jump to.
|
|
static const int kPatchReturnSequenceAddressOffset = 0;
|
|
|
|
// Distance between start of patched debug break slot and the emitted address
|
|
// to jump to.
|
|
static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
|
|
|
|
// Difference between address of current opcode and value read from pc
|
|
// register.
|
|
static const int kPcLoadDelta = 4;
|
|
|
|
// Number of instructions used for the JS return sequence. The constant is
|
|
// used by the debugger to patch the JS return sequence.
|
|
static const int kJSReturnSequenceInstructions = 7;
|
|
static const int kDebugBreakSlotInstructions = 4;
|
|
static const int kDebugBreakSlotLength =
|
|
kDebugBreakSlotInstructions * kInstrSize;
|
|
|
|
|
|
// ---------------------------------------------------------------------------
|
|
// Code generation.
|
|
|
|
// Insert the smallest number of nop instructions
|
|
// possible to align the pc offset to a multiple
|
|
// of m. m must be a power of 2 (>= 4).
|
|
void Align(int m);
|
|
// Aligns code to something that's optimal for a jump target for the platform.
|
|
void CodeTargetAlign();
|
|
|
|
// Different nop operations are used by the code generator to detect certain
|
|
// states of the generated code.
|
|
enum NopMarkerTypes {
|
|
NON_MARKING_NOP = 0,
|
|
DEBUG_BREAK_NOP,
|
|
// IC markers.
|
|
PROPERTY_ACCESS_INLINED,
|
|
PROPERTY_ACCESS_INLINED_CONTEXT,
|
|
PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
|
|
// Helper values.
|
|
LAST_CODE_MARKER,
|
|
FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED
|
|
};
|
|
|
|
// Type == 0 is the default non-marking type.
|
|
void nop(unsigned int type = 0) {
|
|
ASSERT(type < 32);
|
|
sll(zero_reg, zero_reg, type, true);
|
|
}
|
|
|
|
|
|
// --------Branch-and-jump-instructions----------
|
|
// We don't use likely variant of instructions.
|
|
void b(int16_t offset);
|
|
void b(Label* L) { b(branch_offset(L, false)>>2); }
|
|
void bal(int16_t offset);
|
|
void bal(Label* L) { bal(branch_offset(L, false)>>2); }
|
|
|
|
void beq(Register rs, Register rt, int16_t offset);
|
|
void beq(Register rs, Register rt, Label* L) {
|
|
beq(rs, rt, branch_offset(L, false) >> 2);
|
|
}
|
|
void bgez(Register rs, int16_t offset);
|
|
void bgezal(Register rs, int16_t offset);
|
|
void bgtz(Register rs, int16_t offset);
|
|
void blez(Register rs, int16_t offset);
|
|
void bltz(Register rs, int16_t offset);
|
|
void bltzal(Register rs, int16_t offset);
|
|
void bne(Register rs, Register rt, int16_t offset);
|
|
void bne(Register rs, Register rt, Label* L) {
|
|
bne(rs, rt, branch_offset(L, false)>>2);
|
|
}
|
|
|
|
// Never use the int16_t b(l)cond version with a branch offset
|
|
// instead of using the Label* version.
|
|
|
|
// Jump targets must be in the current 256 MB-aligned region. ie 28 bits.
|
|
void j(int32_t target);
|
|
void jal(int32_t target);
|
|
void jalr(Register rs, Register rd = ra);
|
|
void jr(Register target);
|
|
|
|
|
|
//-------Data-processing-instructions---------
|
|
|
|
// Arithmetic.
|
|
void addu(Register rd, Register rs, Register rt);
|
|
void subu(Register rd, Register rs, Register rt);
|
|
void mult(Register rs, Register rt);
|
|
void multu(Register rs, Register rt);
|
|
void div(Register rs, Register rt);
|
|
void divu(Register rs, Register rt);
|
|
void mul(Register rd, Register rs, Register rt);
|
|
|
|
void addiu(Register rd, Register rs, int32_t j);
|
|
|
|
// Logical.
|
|
void and_(Register rd, Register rs, Register rt);
|
|
void or_(Register rd, Register rs, Register rt);
|
|
void xor_(Register rd, Register rs, Register rt);
|
|
void nor(Register rd, Register rs, Register rt);
|
|
|
|
void andi(Register rd, Register rs, int32_t j);
|
|
void ori(Register rd, Register rs, int32_t j);
|
|
void xori(Register rd, Register rs, int32_t j);
|
|
void lui(Register rd, int32_t j);
|
|
|
|
// Shifts.
|
|
// Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop
|
|
// and may cause problems in normal code. coming_from_nop makes sure this
|
|
// doesn't happen.
|
|
void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false);
|
|
void sllv(Register rd, Register rt, Register rs);
|
|
void srl(Register rd, Register rt, uint16_t sa);
|
|
void srlv(Register rd, Register rt, Register rs);
|
|
void sra(Register rt, Register rd, uint16_t sa);
|
|
void srav(Register rt, Register rd, Register rs);
|
|
void rotr(Register rd, Register rt, uint16_t sa);
|
|
void rotrv(Register rd, Register rt, Register rs);
|
|
|
|
|
|
//------------Memory-instructions-------------
|
|
|
|
void lb(Register rd, const MemOperand& rs);
|
|
void lbu(Register rd, const MemOperand& rs);
|
|
void lh(Register rd, const MemOperand& rs);
|
|
void lhu(Register rd, const MemOperand& rs);
|
|
void lw(Register rd, const MemOperand& rs);
|
|
void lwl(Register rd, const MemOperand& rs);
|
|
void lwr(Register rd, const MemOperand& rs);
|
|
void sb(Register rd, const MemOperand& rs);
|
|
void sh(Register rd, const MemOperand& rs);
|
|
void sw(Register rd, const MemOperand& rs);
|
|
void swl(Register rd, const MemOperand& rs);
|
|
void swr(Register rd, const MemOperand& rs);
|
|
|
|
|
|
//-------------Misc-instructions--------------
|
|
|
|
// Break / Trap instructions.
|
|
void break_(uint32_t code, bool break_as_stop = false);
|
|
void stop(const char* msg, uint32_t code = kMaxStopCode);
|
|
void tge(Register rs, Register rt, uint16_t code);
|
|
void tgeu(Register rs, Register rt, uint16_t code);
|
|
void tlt(Register rs, Register rt, uint16_t code);
|
|
void tltu(Register rs, Register rt, uint16_t code);
|
|
void teq(Register rs, Register rt, uint16_t code);
|
|
void tne(Register rs, Register rt, uint16_t code);
|
|
|
|
// Move from HI/LO register.
|
|
void mfhi(Register rd);
|
|
void mflo(Register rd);
|
|
|
|
// Set on less than.
|
|
void slt(Register rd, Register rs, Register rt);
|
|
void sltu(Register rd, Register rs, Register rt);
|
|
void slti(Register rd, Register rs, int32_t j);
|
|
void sltiu(Register rd, Register rs, int32_t j);
|
|
|
|
// Conditional move.
|
|
void movz(Register rd, Register rs, Register rt);
|
|
void movn(Register rd, Register rs, Register rt);
|
|
void movt(Register rd, Register rs, uint16_t cc = 0);
|
|
void movf(Register rd, Register rs, uint16_t cc = 0);
|
|
|
|
// Bit twiddling.
|
|
void clz(Register rd, Register rs);
|
|
void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
|
|
void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
|
|
|
|
//--------Coprocessor-instructions----------------
|
|
|
|
// Load, store, and move.
|
|
void lwc1(FPURegister fd, const MemOperand& src);
|
|
void ldc1(FPURegister fd, const MemOperand& src);
|
|
|
|
void swc1(FPURegister fs, const MemOperand& dst);
|
|
void sdc1(FPURegister fs, const MemOperand& dst);
|
|
|
|
void mtc1(Register rt, FPURegister fs);
|
|
void mfc1(Register rt, FPURegister fs);
|
|
|
|
void ctc1(Register rt, FPUControlRegister fs);
|
|
void cfc1(Register rt, FPUControlRegister fs);
|
|
|
|
// Arithmetic.
|
|
void add_d(FPURegister fd, FPURegister fs, FPURegister ft);
|
|
void sub_d(FPURegister fd, FPURegister fs, FPURegister ft);
|
|
void mul_d(FPURegister fd, FPURegister fs, FPURegister ft);
|
|
void div_d(FPURegister fd, FPURegister fs, FPURegister ft);
|
|
void abs_d(FPURegister fd, FPURegister fs);
|
|
void mov_d(FPURegister fd, FPURegister fs);
|
|
void neg_d(FPURegister fd, FPURegister fs);
|
|
void sqrt_d(FPURegister fd, FPURegister fs);
|
|
|
|
// Conversion.
|
|
void cvt_w_s(FPURegister fd, FPURegister fs);
|
|
void cvt_w_d(FPURegister fd, FPURegister fs);
|
|
void trunc_w_s(FPURegister fd, FPURegister fs);
|
|
void trunc_w_d(FPURegister fd, FPURegister fs);
|
|
void round_w_s(FPURegister fd, FPURegister fs);
|
|
void round_w_d(FPURegister fd, FPURegister fs);
|
|
void floor_w_s(FPURegister fd, FPURegister fs);
|
|
void floor_w_d(FPURegister fd, FPURegister fs);
|
|
void ceil_w_s(FPURegister fd, FPURegister fs);
|
|
void ceil_w_d(FPURegister fd, FPURegister fs);
|
|
|
|
void cvt_l_s(FPURegister fd, FPURegister fs);
|
|
void cvt_l_d(FPURegister fd, FPURegister fs);
|
|
void trunc_l_s(FPURegister fd, FPURegister fs);
|
|
void trunc_l_d(FPURegister fd, FPURegister fs);
|
|
void round_l_s(FPURegister fd, FPURegister fs);
|
|
void round_l_d(FPURegister fd, FPURegister fs);
|
|
void floor_l_s(FPURegister fd, FPURegister fs);
|
|
void floor_l_d(FPURegister fd, FPURegister fs);
|
|
void ceil_l_s(FPURegister fd, FPURegister fs);
|
|
void ceil_l_d(FPURegister fd, FPURegister fs);
|
|
|
|
void cvt_s_w(FPURegister fd, FPURegister fs);
|
|
void cvt_s_l(FPURegister fd, FPURegister fs);
|
|
void cvt_s_d(FPURegister fd, FPURegister fs);
|
|
|
|
void cvt_d_w(FPURegister fd, FPURegister fs);
|
|
void cvt_d_l(FPURegister fd, FPURegister fs);
|
|
void cvt_d_s(FPURegister fd, FPURegister fs);
|
|
|
|
// Conditions and branches.
|
|
void c(FPUCondition cond, SecondaryField fmt,
|
|
FPURegister ft, FPURegister fs, uint16_t cc = 0);
|
|
|
|
void bc1f(int16_t offset, uint16_t cc = 0);
|
|
void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); }
|
|
void bc1t(int16_t offset, uint16_t cc = 0);
|
|
void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
|
|
void fcmp(FPURegister src1, const double src2, FPUCondition cond);
|
|
|
|
// Check the code size generated from label to here.
|
|
int InstructionsGeneratedSince(Label* l) {
|
|
return (pc_offset() - l->pos()) / kInstrSize;
|
|
}
|
|
|
|
// Class for scoping postponing the trampoline pool generation.
|
|
class BlockTrampolinePoolScope {
|
|
public:
|
|
explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) {
|
|
assem_->StartBlockTrampolinePool();
|
|
}
|
|
~BlockTrampolinePoolScope() {
|
|
assem_->EndBlockTrampolinePool();
|
|
}
|
|
|
|
private:
|
|
Assembler* assem_;
|
|
|
|
DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope);
|
|
};
|
|
|
|
// Debugging.
|
|
|
|
// Mark address of the ExitJSFrame code.
|
|
void RecordJSReturn();
|
|
|
|
// Mark address of a debug break slot.
|
|
void RecordDebugBreakSlot();
|
|
|
|
// Record the AST id of the CallIC being compiled, so that it can be placed
|
|
// in the relocation information.
|
|
void RecordAstId(unsigned ast_id) { ast_id_for_reloc_info_ = ast_id; }
|
|
|
|
// Record a comment relocation entry that can be used by a disassembler.
|
|
// Use --code-comments to enable.
|
|
void RecordComment(const char* msg);
|
|
|
|
// Writes a single byte or word of data in the code stream. Used for
|
|
// inline tables, e.g., jump-tables.
|
|
void db(uint8_t data);
|
|
void dd(uint32_t data);
|
|
|
|
int32_t pc_offset() const { return pc_ - buffer_; }
|
|
|
|
PositionsRecorder* positions_recorder() { return &positions_recorder_; }
|
|
|
|
// Postpone the generation of the trampoline pool for the specified number of
|
|
// instructions.
|
|
void BlockTrampolinePoolFor(int instructions);
|
|
|
|
// Check if there is less than kGap bytes available in the buffer.
|
|
// If this is the case, we need to grow the buffer before emitting
|
|
// an instruction or relocation information.
|
|
inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
|
|
|
|
// Get the number of bytes available in the buffer.
|
|
inline int available_space() const { return reloc_info_writer.pos() - pc_; }
|
|
|
|
// Read/patch instructions.
|
|
static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
|
|
static void instr_at_put(byte* pc, Instr instr) {
|
|
*reinterpret_cast<Instr*>(pc) = instr;
|
|
}
|
|
Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
|
|
void instr_at_put(int pos, Instr instr) {
|
|
*reinterpret_cast<Instr*>(buffer_ + pos) = instr;
|
|
}
|
|
|
|
// Check if an instruction is a branch of some kind.
|
|
static bool IsBranch(Instr instr);
|
|
static bool IsBeq(Instr instr);
|
|
static bool IsBne(Instr instr);
|
|
|
|
static bool IsNop(Instr instr, unsigned int type);
|
|
static bool IsPop(Instr instr);
|
|
static bool IsPush(Instr instr);
|
|
static bool IsLwRegFpOffset(Instr instr);
|
|
static bool IsSwRegFpOffset(Instr instr);
|
|
static bool IsLwRegFpNegOffset(Instr instr);
|
|
static bool IsSwRegFpNegOffset(Instr instr);
|
|
|
|
static Register GetRtReg(Instr instr);
|
|
static Register GetRsReg(Instr instr);
|
|
static Register GetRdReg(Instr instr);
|
|
|
|
static uint32_t GetRt(Instr instr);
|
|
static uint32_t GetRtField(Instr instr);
|
|
static uint32_t GetRs(Instr instr);
|
|
static uint32_t GetRsField(Instr instr);
|
|
static uint32_t GetRd(Instr instr);
|
|
static uint32_t GetRdField(Instr instr);
|
|
static uint32_t GetSa(Instr instr);
|
|
static uint32_t GetSaField(Instr instr);
|
|
static uint32_t GetOpcodeField(Instr instr);
|
|
static uint32_t GetImmediate16(Instr instr);
|
|
static uint32_t GetLabelConst(Instr instr);
|
|
|
|
static int32_t GetBranchOffset(Instr instr);
|
|
static bool IsLw(Instr instr);
|
|
static int16_t GetLwOffset(Instr instr);
|
|
static Instr SetLwOffset(Instr instr, int16_t offset);
|
|
|
|
static bool IsSw(Instr instr);
|
|
static Instr SetSwOffset(Instr instr, int16_t offset);
|
|
static bool IsAddImmediate(Instr instr);
|
|
static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
|
|
|
|
static bool IsAndImmediate(Instr instr);
|
|
|
|
void CheckTrampolinePool(bool force_emit = false);
|
|
|
|
protected:
|
|
// Relocation for a type-recording IC has the AST id added to it. This
|
|
// member variable is a way to pass the information from the call site to
|
|
// the relocation info.
|
|
unsigned ast_id_for_reloc_info_;
|
|
|
|
bool emit_debug_code() const { return emit_debug_code_; }
|
|
|
|
int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
|
|
|
|
// Decode branch instruction at pos and return branch target pos.
|
|
int target_at(int32_t pos);
|
|
|
|
// Patch branch instruction at pos to branch to given branch target pos.
|
|
void target_at_put(int32_t pos, int32_t target_pos);
|
|
|
|
// Say if we need to relocate with this mode.
|
|
bool MustUseReg(RelocInfo::Mode rmode);
|
|
|
|
// Record reloc info for current pc_.
|
|
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
|
|
|
|
// Block the emission of the trampoline pool before pc_offset.
|
|
void BlockTrampolinePoolBefore(int pc_offset) {
|
|
if (no_trampoline_pool_before_ < pc_offset)
|
|
no_trampoline_pool_before_ = pc_offset;
|
|
}
|
|
|
|
void StartBlockTrampolinePool() {
|
|
trampoline_pool_blocked_nesting_++;
|
|
}
|
|
void EndBlockTrampolinePool() {
|
|
trampoline_pool_blocked_nesting_--;
|
|
}
|
|
|
|
bool is_trampoline_pool_blocked() const {
|
|
return trampoline_pool_blocked_nesting_ > 0;
|
|
}
|
|
|
|
bool has_exception() const {
|
|
return internal_trampoline_exception_;
|
|
}
|
|
|
|
private:
|
|
// Code buffer:
|
|
// The buffer into which code and relocation info are generated.
|
|
byte* buffer_;
|
|
int buffer_size_;
|
|
// True if the assembler owns the buffer, false if buffer is external.
|
|
bool own_buffer_;
|
|
|
|
// Buffer size and constant pool distance are checked together at regular
|
|
// intervals of kBufferCheckInterval emitted bytes.
|
|
static const int kBufferCheckInterval = 1*KB/2;
|
|
|
|
// Code generation.
|
|
// The relocation writer's position is at least kGap bytes below the end of
|
|
// the generated instructions. This is so that multi-instruction sequences do
|
|
// not have to check for overflow. The same is true for writes of large
|
|
// relocation info entries.
|
|
static const int kGap = 32;
|
|
byte* pc_; // The program counter - moves forward.
|
|
|
|
|
|
// Repeated checking whether the trampoline pool should be emitted is rather
|
|
// expensive. By default we only check again once a number of instructions
|
|
// has been generated.
|
|
static const int kCheckConstIntervalInst = 32;
|
|
static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
|
|
|
|
int next_buffer_check_; // pc offset of next buffer check.
|
|
|
|
// Emission of the trampoline pool may be blocked in some code sequences.
|
|
int trampoline_pool_blocked_nesting_; // Block emission if this is not zero.
|
|
int no_trampoline_pool_before_; // Block emission before this pc offset.
|
|
|
|
// Keep track of the last emitted pool to guarantee a maximal distance.
|
|
int last_trampoline_pool_end_; // pc offset of the end of the last pool.
|
|
|
|
// Relocation information generation.
|
|
// Each relocation is encoded as a variable size value.
|
|
static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
|
|
RelocInfoWriter reloc_info_writer;
|
|
|
|
// The bound position, before this we cannot do instruction elimination.
|
|
int last_bound_pos_;
|
|
|
|
// Code emission.
|
|
inline void CheckBuffer();
|
|
void GrowBuffer();
|
|
inline void emit(Instr x);
|
|
inline void CheckTrampolinePoolQuick();
|
|
|
|
// Instruction generation.
|
|
// We have 3 different kind of encoding layout on MIPS.
|
|
// However due to many different types of objects encoded in the same fields
|
|
// we have quite a few aliases for each mode.
|
|
// Using the same structure to refer to Register and FPURegister would spare a
|
|
// few aliases, but mixing both does not look clean to me.
|
|
// Anyway we could surely implement this differently.
|
|
|
|
void GenInstrRegister(Opcode opcode,
|
|
Register rs,
|
|
Register rt,
|
|
Register rd,
|
|
uint16_t sa = 0,
|
|
SecondaryField func = NULLSF);
|
|
|
|
void GenInstrRegister(Opcode opcode,
|
|
Register rs,
|
|
Register rt,
|
|
uint16_t msb,
|
|
uint16_t lsb,
|
|
SecondaryField func);
|
|
|
|
void GenInstrRegister(Opcode opcode,
|
|
SecondaryField fmt,
|
|
FPURegister ft,
|
|
FPURegister fs,
|
|
FPURegister fd,
|
|
SecondaryField func = NULLSF);
|
|
|
|
void GenInstrRegister(Opcode opcode,
|
|
SecondaryField fmt,
|
|
Register rt,
|
|
FPURegister fs,
|
|
FPURegister fd,
|
|
SecondaryField func = NULLSF);
|
|
|
|
void GenInstrRegister(Opcode opcode,
|
|
SecondaryField fmt,
|
|
Register rt,
|
|
FPUControlRegister fs,
|
|
SecondaryField func = NULLSF);
|
|
|
|
|
|
void GenInstrImmediate(Opcode opcode,
|
|
Register rs,
|
|
Register rt,
|
|
int32_t j);
|
|
void GenInstrImmediate(Opcode opcode,
|
|
Register rs,
|
|
SecondaryField SF,
|
|
int32_t j);
|
|
void GenInstrImmediate(Opcode opcode,
|
|
Register r1,
|
|
FPURegister r2,
|
|
int32_t j);
|
|
|
|
|
|
void GenInstrJump(Opcode opcode,
|
|
uint32_t address);
|
|
|
|
// Helpers.
|
|
void LoadRegPlusOffsetToAt(const MemOperand& src);
|
|
|
|
// Labels.
|
|
void print(Label* L);
|
|
void bind_to(Label* L, int pos);
|
|
void link_to(Label* L, Label* appendix);
|
|
void next(Label* L);
|
|
|
|
// One trampoline consists of:
|
|
// - space for trampoline slots,
|
|
// - space for labels.
|
|
//
|
|
// Space for trampoline slots is equal to slot_count * 2 * kInstrSize.
|
|
// Space for trampoline slots preceeds space for labels. Each label is of one
|
|
// instruction size, so total amount for labels is equal to
|
|
// label_count * kInstrSize.
|
|
class Trampoline {
|
|
public:
|
|
Trampoline(int start, int slot_count, int label_count) {
|
|
start_ = start;
|
|
next_slot_ = start;
|
|
free_slot_count_ = slot_count;
|
|
next_label_ = start + slot_count * 2 * kInstrSize;
|
|
free_label_count_ = label_count;
|
|
end_ = next_label_ + (label_count - 1) * kInstrSize;
|
|
}
|
|
int start() {
|
|
return start_;
|
|
}
|
|
int end() {
|
|
return end_;
|
|
}
|
|
int take_slot() {
|
|
int trampoline_slot = kInvalidSlotPos;
|
|
if (free_slot_count_ <= 0) {
|
|
// We have run out of space on trampolines.
|
|
// Make sure we fail in debug mode, so we become aware of each case
|
|
// when this happens.
|
|
ASSERT(0);
|
|
// Internal exception will be caught.
|
|
} else {
|
|
trampoline_slot = next_slot_;
|
|
free_slot_count_--;
|
|
next_slot_ += 2*kInstrSize;
|
|
}
|
|
return trampoline_slot;
|
|
}
|
|
int take_label() {
|
|
int label_pos = next_label_;
|
|
ASSERT(free_label_count_ > 0);
|
|
free_label_count_--;
|
|
next_label_ += kInstrSize;
|
|
return label_pos;
|
|
}
|
|
|
|
private:
|
|
int start_;
|
|
int end_;
|
|
int next_slot_;
|
|
int free_slot_count_;
|
|
int next_label_;
|
|
int free_label_count_;
|
|
};
|
|
|
|
int32_t get_label_entry(int32_t pos, bool next_pool = true);
|
|
int32_t get_trampoline_entry(int32_t pos, bool next_pool = true);
|
|
|
|
static const int kSlotsPerTrampoline = 2304;
|
|
static const int kLabelsPerTrampoline = 8;
|
|
static const int kTrampolineInst =
|
|
2 * kSlotsPerTrampoline + kLabelsPerTrampoline;
|
|
static const int kTrampolineSize = kTrampolineInst * kInstrSize;
|
|
static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
|
|
static const int kMaxDistBetweenPools =
|
|
kMaxBranchOffset - 2 * kTrampolineSize;
|
|
static const int kInvalidSlotPos = -1;
|
|
|
|
List<Trampoline> trampolines_;
|
|
bool internal_trampoline_exception_;
|
|
|
|
friend class RegExpMacroAssemblerMIPS;
|
|
friend class RelocInfo;
|
|
friend class CodePatcher;
|
|
friend class BlockTrampolinePoolScope;
|
|
|
|
PositionsRecorder positions_recorder_;
|
|
bool emit_debug_code_;
|
|
friend class PositionsRecorder;
|
|
friend class EnsureSpace;
|
|
};
|
|
|
|
|
|
class EnsureSpace BASE_EMBEDDED {
|
|
public:
|
|
explicit EnsureSpace(Assembler* assembler) {
|
|
assembler->CheckBuffer();
|
|
}
|
|
};
|
|
|
|
} } // namespace v8::internal
|
|
|
|
#endif // V8_ARM_ASSEMBLER_MIPS_H_
|