adb7e37b28
In the Crankshaft days we (mis)used the Representation to also express the various internal representations that the compiler understands. But with TurboFan we now have proper MachineRepresentation and MachineType, which do that independently. So there's no need to have this in the Representation class anymore, and instead the Representation class only needs to deal with the field representations. Bug: v8:8749, v8:8834, v8:8865 Change-Id: I34ea9558b5fdf20d6c7939b52762eaffd4316b06 Reviewed-on: https://chromium-review.googlesource.com/c/1479954 Commit-Queue: Benedikt Meurer <bmeurer@chromium.org> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#59750}
317 lines
10 KiB
C++
317 lines
10 KiB
C++
// Copyright 2013 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <stdlib.h>
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#include "src/assembler-inl.h"
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#include "src/macro-assembler.h"
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#include "src/objects-inl.h"
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#include "src/ostreams.h"
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#include "src/simulator.h"
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#include "src/v8.h"
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#include "test/cctest/cctest.h"
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#include "test/common/assembler-tester.h"
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namespace v8 {
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namespace internal {
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namespace test_macro_assembler_arm {
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using F = void*(int x, int y, int p2, int p3, int p4);
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#define __ masm->
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using F3 = void*(void* p0, int p1, int p2, int p3, int p4);
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using F5 = int(void*, void*, void*, void*, void*);
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TEST(ExtractLane) {
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if (!CpuFeatures::IsSupported(NEON)) return;
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Isolate* isolate = CcTest::i_isolate();
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HandleScope handles(isolate);
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auto buffer = AllocateAssemblerBuffer();
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MacroAssembler assembler(isolate, v8::internal::CodeObjectRequired::kYes,
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buffer->CreateView());
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MacroAssembler* masm = &assembler; // Create a pointer for the __ macro.
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typedef struct {
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int32_t i32x4_low[4];
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int32_t i32x4_high[4];
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int32_t i16x8_low[8];
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int32_t i16x8_high[8];
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int32_t i8x16_low[16];
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int32_t i8x16_high[16];
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int32_t f32x4_low[4];
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int32_t f32x4_high[4];
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int32_t i8x16_low_d[16];
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int32_t i8x16_high_d[16];
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} T;
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T t;
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__ stm(db_w, sp, r4.bit() | r5.bit() | lr.bit());
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for (int i = 0; i < 4; i++) {
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__ mov(r4, Operand(i));
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__ vdup(Neon32, q1, r4);
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__ ExtractLane(r5, q1, NeonS32, i);
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__ str(r5, MemOperand(r0, offsetof(T, i32x4_low) + 4 * i));
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SwVfpRegister si = SwVfpRegister::from_code(i);
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__ ExtractLane(si, q1, i);
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__ vstr(si, r0, offsetof(T, f32x4_low) + 4 * i);
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}
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for (int i = 0; i < 8; i++) {
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__ mov(r4, Operand(i));
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__ vdup(Neon16, q1, r4);
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__ ExtractLane(r5, q1, NeonS16, i);
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__ str(r5, MemOperand(r0, offsetof(T, i16x8_low) + 4 * i));
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}
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for (int i = 0; i < 16; i++) {
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__ mov(r4, Operand(i));
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__ vdup(Neon8, q1, r4);
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__ ExtractLane(r5, q1, NeonS8, i);
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__ str(r5, MemOperand(r0, offsetof(T, i8x16_low) + 4 * i));
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}
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for (int i = 0; i < 8; i++) {
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__ mov(r4, Operand(i));
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__ vdup(Neon8, q1, r4); // q1 = d2,d3
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__ ExtractLane(r5, d2, NeonS8, i);
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__ str(r5, MemOperand(r0, offsetof(T, i8x16_low_d) + 4 * i));
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__ ExtractLane(r5, d3, NeonS8, i);
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__ str(r5, MemOperand(r0, offsetof(T, i8x16_low_d) + 4 * (i + 8)));
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}
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if (CpuFeatures::IsSupported(VFP32DREGS)) {
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for (int i = 0; i < 4; i++) {
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__ mov(r4, Operand(-i));
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__ vdup(Neon32, q15, r4);
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__ ExtractLane(r5, q15, NeonS32, i);
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__ str(r5, MemOperand(r0, offsetof(T, i32x4_high) + 4 * i));
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SwVfpRegister si = SwVfpRegister::from_code(i);
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__ ExtractLane(si, q15, i);
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__ vstr(si, r0, offsetof(T, f32x4_high) + 4 * i);
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}
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for (int i = 0; i < 8; i++) {
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__ mov(r4, Operand(-i));
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__ vdup(Neon16, q15, r4);
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__ ExtractLane(r5, q15, NeonS16, i);
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__ str(r5, MemOperand(r0, offsetof(T, i16x8_high) + 4 * i));
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}
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for (int i = 0; i < 16; i++) {
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__ mov(r4, Operand(-i));
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__ vdup(Neon8, q15, r4);
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__ ExtractLane(r5, q15, NeonS8, i);
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__ str(r5, MemOperand(r0, offsetof(T, i8x16_high) + 4 * i));
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}
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for (int i = 0; i < 8; i++) {
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__ mov(r4, Operand(-i));
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__ vdup(Neon8, q15, r4); // q1 = d30,d31
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__ ExtractLane(r5, d30, NeonS8, i);
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__ str(r5, MemOperand(r0, offsetof(T, i8x16_high_d) + 4 * i));
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__ ExtractLane(r5, d31, NeonS8, i);
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__ str(r5, MemOperand(r0, offsetof(T, i8x16_high_d) + 4 * (i + 8)));
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}
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}
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__ ldm(ia_w, sp, r4.bit() | r5.bit() | pc.bit());
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CodeDesc desc;
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masm->GetCode(isolate, &desc);
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Handle<Code> code =
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isolate->factory()->NewCode(desc, Code::STUB, Handle<Code>());
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#ifdef DEBUG
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StdoutStream os;
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code->Print(os);
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#endif
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auto f = GeneratedCode<F3>::FromCode(*code);
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f.Call(&t, 0, 0, 0, 0);
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for (int i = 0; i < 4; i++) {
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CHECK_EQ(i, t.i32x4_low[i]);
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CHECK_EQ(i, t.f32x4_low[i]);
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}
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for (int i = 0; i < 8; i++) {
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CHECK_EQ(i, t.i16x8_low[i]);
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}
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for (int i = 0; i < 16; i++) {
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CHECK_EQ(i, t.i8x16_low[i]);
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}
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for (int i = 0; i < 8; i++) {
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CHECK_EQ(i, t.i8x16_low_d[i]);
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CHECK_EQ(i, t.i8x16_low_d[i + 8]);
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}
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if (CpuFeatures::IsSupported(VFP32DREGS)) {
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for (int i = 0; i < 4; i++) {
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CHECK_EQ(-i, t.i32x4_high[i]);
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CHECK_EQ(-i, t.f32x4_high[i]);
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}
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for (int i = 0; i < 8; i++) {
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CHECK_EQ(-i, t.i16x8_high[i]);
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}
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for (int i = 0; i < 16; i++) {
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CHECK_EQ(-i, t.i8x16_high[i]);
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}
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for (int i = 0; i < 8; i++) {
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CHECK_EQ(-i, t.i8x16_high_d[i]);
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CHECK_EQ(-i, t.i8x16_high_d[i + 8]);
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}
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}
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}
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TEST(ReplaceLane) {
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if (!CpuFeatures::IsSupported(NEON)) return;
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Isolate* isolate = CcTest::i_isolate();
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HandleScope handles(isolate);
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auto buffer = AllocateAssemblerBuffer();
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MacroAssembler assembler(isolate, v8::internal::CodeObjectRequired::kYes,
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buffer->CreateView());
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MacroAssembler* masm = &assembler; // Create a pointer for the __ macro.
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typedef struct {
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int32_t i32x4_low[4];
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int32_t i32x4_high[4];
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int16_t i16x8_low[8];
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int16_t i16x8_high[8];
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int8_t i8x16_low[16];
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int8_t i8x16_high[16];
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int32_t f32x4_low[4];
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int32_t f32x4_high[4];
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} T;
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T t;
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__ stm(db_w, sp, r4.bit() | r5.bit() | r6.bit() | r7.bit() | lr.bit());
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__ veor(q0, q0, q0); // Zero
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__ veor(q1, q1, q1); // Zero
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for (int i = 0; i < 4; i++) {
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__ mov(r4, Operand(i));
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__ ReplaceLane(q0, q0, r4, NeonS32, i);
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SwVfpRegister si = SwVfpRegister::from_code(i);
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__ vmov(si, r4);
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__ ReplaceLane(q1, q1, si, i);
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}
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__ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, i32x4_low))));
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__ vst1(Neon8, NeonListOperand(q0), NeonMemOperand(r4));
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__ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, f32x4_low))));
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__ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
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__ veor(q0, q0, q0); // Zero
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for (int i = 0; i < 8; i++) {
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__ mov(r4, Operand(i));
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__ ReplaceLane(q0, q0, r4, NeonS16, i);
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}
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__ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, i16x8_low))));
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__ vst1(Neon8, NeonListOperand(q0), NeonMemOperand(r4));
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__ veor(q0, q0, q0); // Zero
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for (int i = 0; i < 16; i++) {
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__ mov(r4, Operand(i));
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__ ReplaceLane(q0, q0, r4, NeonS8, i);
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}
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__ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, i8x16_low))));
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__ vst1(Neon8, NeonListOperand(q0), NeonMemOperand(r4));
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if (CpuFeatures::IsSupported(VFP32DREGS)) {
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__ veor(q14, q14, q14); // Zero
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__ veor(q15, q15, q15); // Zero
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for (int i = 0; i < 4; i++) {
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__ mov(r4, Operand(-i));
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__ ReplaceLane(q14, q14, r4, NeonS32, i);
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SwVfpRegister si = SwVfpRegister::from_code(i);
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__ vmov(si, r4);
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__ ReplaceLane(q15, q15, si, i);
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}
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__ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, i32x4_high))));
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__ vst1(Neon8, NeonListOperand(q14), NeonMemOperand(r4));
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__ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, f32x4_high))));
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__ vst1(Neon8, NeonListOperand(q15), NeonMemOperand(r4));
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__ veor(q14, q14, q14); // Zero
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for (int i = 0; i < 8; i++) {
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__ mov(r4, Operand(-i));
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__ ReplaceLane(q14, q14, r4, NeonS16, i);
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}
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__ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, i16x8_high))));
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__ vst1(Neon8, NeonListOperand(q14), NeonMemOperand(r4));
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__ veor(q14, q14, q14); // Zero
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for (int i = 0; i < 16; i++) {
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__ mov(r4, Operand(-i));
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__ ReplaceLane(q14, q14, r4, NeonS8, i);
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}
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__ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, i8x16_high))));
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__ vst1(Neon8, NeonListOperand(q14), NeonMemOperand(r4));
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}
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__ ldm(ia_w, sp, r4.bit() | r5.bit() | r6.bit() | r7.bit() | pc.bit());
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CodeDesc desc;
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masm->GetCode(isolate, &desc);
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Handle<Code> code =
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isolate->factory()->NewCode(desc, Code::STUB, Handle<Code>());
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#ifdef DEBUG
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StdoutStream os;
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code->Print(os);
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#endif
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auto f = GeneratedCode<F3>::FromCode(*code);
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f.Call(&t, 0, 0, 0, 0);
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for (int i = 0; i < 4; i++) {
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CHECK_EQ(i, t.i32x4_low[i]);
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CHECK_EQ(i, t.f32x4_low[i]);
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}
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for (int i = 0; i < 8; i++) {
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CHECK_EQ(i, t.i16x8_low[i]);
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}
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for (int i = 0; i < 16; i++) {
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CHECK_EQ(i, t.i8x16_low[i]);
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}
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if (CpuFeatures::IsSupported(VFP32DREGS)) {
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for (int i = 0; i < 4; i++) {
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CHECK_EQ(-i, t.i32x4_high[i]);
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CHECK_EQ(-i, t.f32x4_high[i]);
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}
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for (int i = 0; i < 8; i++) {
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CHECK_EQ(-i, t.i16x8_high[i]);
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}
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for (int i = 0; i < 16; i++) {
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CHECK_EQ(-i, t.i8x16_high[i]);
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}
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}
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}
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#undef __
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} // namespace test_macro_assembler_arm
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} // namespace internal
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} // namespace v8
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