Lu Yahan f4782ed4bb [riscv64] Uint32 sign extend into 64bit ... The intent of the RISC-V ISA is that 32-bit C values are stored sign extended in registers, even for unsigned types. So we skip cctest case RunLoadStoreZeroExtend64/RunUnalignedLoadStoreZeroExtend64 due to sign extend uint32 Change-Id: Icfe727916b1c04aad5681902ec4782cc98906964 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3184560 Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by: Michael Achenbach <machenbach@chromium.org> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77112}		2021-09-28 11:39:26 +00:00
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instruction-selector-riscv64-unittest.cc	[riscv64] Uint32 sign extend into 64bit	2021-09-28 11:39:26 +00:00