ba12ca16a2
TEST=cctest/test-run-machops,cctest/test-instruction-selector-arm R=titzer@chromium.org Review URL: https://codereview.chromium.org/432373002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22791 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
1756 lines
63 KiB
C++
1756 lines
63 KiB
C++
// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#include <list>
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#include "test/cctest/compiler/instruction-selector-tester.h"
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#include "test/cctest/compiler/value-helper.h"
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using namespace v8::internal;
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using namespace v8::internal::compiler;
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namespace {
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typedef RawMachineAssembler::Label MLabel;
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struct DPI {
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Operator* op;
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ArchOpcode arch_opcode;
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ArchOpcode reverse_arch_opcode;
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ArchOpcode test_arch_opcode;
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};
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// ARM data processing instructions.
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class DPIs V8_FINAL : public std::list<DPI>, private HandleAndZoneScope {
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public:
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DPIs() {
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MachineOperatorBuilder machine(main_zone());
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DPI and_ = {machine.Word32And(), kArmAnd, kArmAnd, kArmTst};
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push_back(and_);
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DPI or_ = {machine.Word32Or(), kArmOrr, kArmOrr, kArmOrr};
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push_back(or_);
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DPI xor_ = {machine.Word32Xor(), kArmEor, kArmEor, kArmTeq};
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push_back(xor_);
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DPI add = {machine.Int32Add(), kArmAdd, kArmAdd, kArmCmn};
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push_back(add);
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DPI sub = {machine.Int32Sub(), kArmSub, kArmRsb, kArmCmp};
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push_back(sub);
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}
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};
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struct ODPI {
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Operator* op;
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ArchOpcode arch_opcode;
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ArchOpcode reverse_arch_opcode;
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};
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// ARM data processing instructions with overflow.
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class ODPIs V8_FINAL : public std::list<ODPI>, private HandleAndZoneScope {
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public:
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ODPIs() {
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MachineOperatorBuilder machine(main_zone());
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ODPI add = {machine.Int32AddWithOverflow(), kArmAdd, kArmAdd};
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push_back(add);
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ODPI sub = {machine.Int32SubWithOverflow(), kArmSub, kArmRsb};
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push_back(sub);
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}
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};
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// ARM immediates.
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class Immediates V8_FINAL : public std::list<int32_t> {
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public:
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Immediates() {
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for (uint32_t imm8 = 0; imm8 < 256; ++imm8) {
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for (uint32_t rot4 = 0; rot4 < 32; rot4 += 2) {
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int32_t imm = (imm8 >> rot4) | (imm8 << (32 - rot4));
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CHECK(Assembler::ImmediateFitsAddrMode1Instruction(imm));
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push_back(imm);
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}
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}
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}
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};
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struct Shift {
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Operator* op;
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int32_t i_low; // lowest possible immediate
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int32_t i_high; // highest possible immediate
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AddressingMode i_mode; // Operand2_R_<shift>_I
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AddressingMode r_mode; // Operand2_R_<shift>_R
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};
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// ARM shifts.
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class Shifts V8_FINAL : public std::list<Shift>, private HandleAndZoneScope {
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public:
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Shifts() {
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MachineOperatorBuilder machine(main_zone());
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Shift sar = {machine.Word32Sar(), 1, 32, kMode_Operand2_R_ASR_I,
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kMode_Operand2_R_ASR_R};
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Shift shl = {machine.Word32Shl(), 0, 31, kMode_Operand2_R_LSL_I,
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kMode_Operand2_R_LSL_R};
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Shift shr = {machine.Word32Shr(), 1, 32, kMode_Operand2_R_LSR_I,
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kMode_Operand2_R_LSR_R};
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push_back(sar);
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push_back(shl);
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push_back(shr);
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}
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};
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} // namespace
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TEST(InstructionSelectorDPIP) {
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DPIs dpis;
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for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
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DPI dpi = *i;
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InstructionSelectorTester m;
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m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Parameter(1)));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
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}
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}
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TEST(InstructionSelectorDPIAndShiftP) {
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DPIs dpis;
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Shifts shifts;
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for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
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DPI dpi = *i;
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for (Shifts::const_iterator j = shifts.begin(); j != shifts.end(); ++j) {
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Shift shift = *j;
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{
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InstructionSelectorTester m;
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m.Return(
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m.NewNode(dpi.op, m.Parameter(0),
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m.NewNode(shift.op, m.Parameter(1), m.Parameter(2))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
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}
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{
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InstructionSelectorTester m;
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m.Return(m.NewNode(dpi.op,
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m.NewNode(shift.op, m.Parameter(0), m.Parameter(1)),
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m.Parameter(2)));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
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}
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}
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}
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}
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TEST(InstructionSelectorDPIAndRotateRightP) {
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DPIs dpis;
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for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
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DPI dpi = *i;
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{
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InstructionSelectorTester m;
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Node* value = m.Parameter(1);
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Node* shift = m.Parameter(2);
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Node* ror = m.Word32Or(
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m.Word32Shr(value, shift),
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m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift)));
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m.Return(m.NewNode(dpi.op, m.Parameter(0), ror));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
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}
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{
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InstructionSelectorTester m;
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Node* value = m.Parameter(1);
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Node* shift = m.Parameter(2);
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Node* ror =
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m.Word32Or(m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift)),
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m.Word32Shr(value, shift));
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m.Return(m.NewNode(dpi.op, m.Parameter(0), ror));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
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}
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{
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InstructionSelectorTester m;
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Node* value = m.Parameter(1);
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Node* shift = m.Parameter(2);
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Node* ror = m.Word32Or(
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m.Word32Shr(value, shift),
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m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift)));
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m.Return(m.NewNode(dpi.op, ror, m.Parameter(0)));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
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}
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{
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InstructionSelectorTester m;
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Node* value = m.Parameter(1);
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Node* shift = m.Parameter(2);
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Node* ror =
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m.Word32Or(m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift)),
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m.Word32Shr(value, shift));
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m.Return(m.NewNode(dpi.op, ror, m.Parameter(0)));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
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}
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}
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}
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TEST(InstructionSelectorDPIAndShiftImm) {
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DPIs dpis;
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Shifts shifts;
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for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
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DPI dpi = *i;
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for (Shifts::const_iterator j = shifts.begin(); j != shifts.end(); ++j) {
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Shift shift = *j;
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for (int32_t imm = shift.i_low; imm <= shift.i_high; ++imm) {
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{
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InstructionSelectorTester m;
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m.Return(m.NewNode(
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dpi.op, m.Parameter(0),
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m.NewNode(shift.op, m.Parameter(1), m.Int32Constant(imm))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
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}
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{
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InstructionSelectorTester m;
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m.Return(m.NewNode(
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dpi.op, m.NewNode(shift.op, m.Parameter(0), m.Int32Constant(imm)),
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m.Parameter(1)));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
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}
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}
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}
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}
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}
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TEST(InstructionSelectorODPIP) {
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ODPIs odpis;
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for (ODPIs::const_iterator i = odpis.begin(); i != odpis.end(); ++i) {
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ODPI odpi = *i;
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{
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InstructionSelectorTester m;
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m.Return(
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m.Projection(1, m.NewNode(odpi.op, m.Parameter(0), m.Parameter(1))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
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CHECK_EQ(kOverflow, m.code[0]->flags_condition());
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CHECK_EQ(2, m.code[0]->InputCount());
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CHECK_EQ(1, m.code[0]->OutputCount());
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}
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{
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InstructionSelectorTester m;
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m.Return(
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m.Projection(0, m.NewNode(odpi.op, m.Parameter(0), m.Parameter(1))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_none, m.code[0]->flags_mode());
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CHECK_EQ(2, m.code[0]->InputCount());
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CHECK_EQ(1, m.code[0]->OutputCount());
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}
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{
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InstructionSelectorTester m;
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Node* node = m.NewNode(odpi.op, m.Parameter(0), m.Parameter(1));
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m.Return(m.Word32Equal(m.Projection(0, node), m.Projection(1, node)));
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m.SelectInstructions();
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CHECK_LE(1, m.code.size());
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CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
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CHECK_EQ(kOverflow, m.code[0]->flags_condition());
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CHECK_EQ(2, m.code[0]->InputCount());
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CHECK_EQ(2, m.code[0]->OutputCount());
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}
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}
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}
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TEST(InstructionSelectorODPIImm) {
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ODPIs odpis;
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Immediates immediates;
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for (ODPIs::const_iterator i = odpis.begin(); i != odpis.end(); ++i) {
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ODPI odpi = *i;
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for (Immediates::const_iterator j = immediates.begin();
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j != immediates.end(); ++j) {
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int32_t imm = *j;
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{
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InstructionSelectorTester m;
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m.Return(m.Projection(
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1, m.NewNode(odpi.op, m.Parameter(0), m.Int32Constant(imm))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
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CHECK_EQ(kOverflow, m.code[0]->flags_condition());
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CHECK_EQ(2, m.code[0]->InputCount());
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CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
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CHECK_EQ(1, m.code[0]->OutputCount());
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}
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{
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InstructionSelectorTester m;
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m.Return(m.Projection(
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1, m.NewNode(odpi.op, m.Int32Constant(imm), m.Parameter(0))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
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CHECK_EQ(kOverflow, m.code[0]->flags_condition());
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CHECK_EQ(2, m.code[0]->InputCount());
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CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
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CHECK_EQ(1, m.code[0]->OutputCount());
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}
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{
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InstructionSelectorTester m;
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m.Return(m.Projection(
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0, m.NewNode(odpi.op, m.Parameter(0), m.Int32Constant(imm))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_none, m.code[0]->flags_mode());
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CHECK_EQ(2, m.code[0]->InputCount());
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CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
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CHECK_EQ(1, m.code[0]->OutputCount());
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}
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{
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InstructionSelectorTester m;
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m.Return(m.Projection(
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0, m.NewNode(odpi.op, m.Int32Constant(imm), m.Parameter(0))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_none, m.code[0]->flags_mode());
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CHECK_EQ(2, m.code[0]->InputCount());
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CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
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CHECK_EQ(1, m.code[0]->OutputCount());
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}
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{
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InstructionSelectorTester m;
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Node* node = m.NewNode(odpi.op, m.Parameter(0), m.Int32Constant(imm));
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m.Return(m.Word32Equal(m.Projection(0, node), m.Projection(1, node)));
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m.SelectInstructions();
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CHECK_LE(1, m.code.size());
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CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
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CHECK_EQ(kOverflow, m.code[0]->flags_condition());
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CHECK_EQ(2, m.code[0]->InputCount());
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CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
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CHECK_EQ(2, m.code[0]->OutputCount());
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}
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{
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InstructionSelectorTester m;
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Node* node = m.NewNode(odpi.op, m.Int32Constant(imm), m.Parameter(0));
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m.Return(m.Word32Equal(m.Projection(0, node), m.Projection(1, node)));
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m.SelectInstructions();
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CHECK_LE(1, m.code.size());
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CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
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CHECK_EQ(kOverflow, m.code[0]->flags_condition());
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CHECK_EQ(2, m.code[0]->InputCount());
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CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
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CHECK_EQ(2, m.code[0]->OutputCount());
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}
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}
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}
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}
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TEST(InstructionSelectorODPIAndShiftP) {
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ODPIs odpis;
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Shifts shifts;
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for (ODPIs::const_iterator i = odpis.begin(); i != odpis.end(); ++i) {
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ODPI odpi = *i;
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for (Shifts::const_iterator j = shifts.begin(); j != shifts.end(); ++j) {
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Shift shift = *j;
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{
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InstructionSelectorTester m;
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m.Return(m.Projection(
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1, m.NewNode(odpi.op, m.Parameter(0),
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m.NewNode(shift.op, m.Parameter(1), m.Parameter(2)))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
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CHECK_EQ(kOverflow, m.code[0]->flags_condition());
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CHECK_EQ(3, m.code[0]->InputCount());
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CHECK_EQ(1, m.code[0]->OutputCount());
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}
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{
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InstructionSelectorTester m;
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m.Return(m.Projection(
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1, m.NewNode(odpi.op,
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m.NewNode(shift.op, m.Parameter(0), m.Parameter(1)),
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m.Parameter(2))));
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m.SelectInstructions();
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CHECK_EQ(1, m.code.size());
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CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
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CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
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CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
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CHECK_EQ(kOverflow, m.code[0]->flags_condition());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Projection(
|
|
0, m.NewNode(odpi.op, m.Parameter(0),
|
|
m.NewNode(shift.op, m.Parameter(1), m.Parameter(2)))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_none, m.code[0]->flags_mode());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Projection(
|
|
0, m.NewNode(odpi.op,
|
|
m.NewNode(shift.op, m.Parameter(0), m.Parameter(1)),
|
|
m.Parameter(2))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_none, m.code[0]->flags_mode());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
Node* node =
|
|
m.NewNode(odpi.op, m.Parameter(0),
|
|
m.NewNode(shift.op, m.Parameter(1), m.Parameter(2)));
|
|
m.Return(m.Word32Equal(m.Projection(0, node), m.Projection(1, node)));
|
|
m.SelectInstructions();
|
|
CHECK_LE(1, m.code.size());
|
|
CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kOverflow, m.code[0]->flags_condition());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(2, m.code[0]->OutputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
Node* node = m.NewNode(
|
|
odpi.op, m.NewNode(shift.op, m.Parameter(0), m.Parameter(1)),
|
|
m.Parameter(2));
|
|
m.Return(m.Word32Equal(m.Projection(0, node), m.Projection(1, node)));
|
|
m.SelectInstructions();
|
|
CHECK_LE(1, m.code.size());
|
|
CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kOverflow, m.code[0]->flags_condition());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(2, m.code[0]->OutputCount());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorODPIAndShiftImm) {
|
|
ODPIs odpis;
|
|
Shifts shifts;
|
|
for (ODPIs::const_iterator i = odpis.begin(); i != odpis.end(); ++i) {
|
|
ODPI odpi = *i;
|
|
for (Shifts::const_iterator j = shifts.begin(); j != shifts.end(); ++j) {
|
|
Shift shift = *j;
|
|
for (int32_t imm = shift.i_low; imm <= shift.i_high; ++imm) {
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Projection(1, m.NewNode(odpi.op, m.Parameter(0),
|
|
m.NewNode(shift.op, m.Parameter(1),
|
|
m.Int32Constant(imm)))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kOverflow, m.code[0]->flags_condition());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(2)));
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Projection(
|
|
1, m.NewNode(odpi.op, m.NewNode(shift.op, m.Parameter(0),
|
|
m.Int32Constant(imm)),
|
|
m.Parameter(1))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kOverflow, m.code[0]->flags_condition());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(2)));
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Projection(0, m.NewNode(odpi.op, m.Parameter(0),
|
|
m.NewNode(shift.op, m.Parameter(1),
|
|
m.Int32Constant(imm)))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_none, m.code[0]->flags_mode());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(2)));
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Projection(
|
|
0, m.NewNode(odpi.op, m.NewNode(shift.op, m.Parameter(0),
|
|
m.Int32Constant(imm)),
|
|
m.Parameter(1))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_none, m.code[0]->flags_mode());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(2)));
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
Node* node = m.NewNode(
|
|
odpi.op, m.Parameter(0),
|
|
m.NewNode(shift.op, m.Parameter(1), m.Int32Constant(imm)));
|
|
m.Return(m.Word32Equal(m.Projection(0, node), m.Projection(1, node)));
|
|
m.SelectInstructions();
|
|
CHECK_LE(1, m.code.size());
|
|
CHECK_EQ(odpi.arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kOverflow, m.code[0]->flags_condition());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(2)));
|
|
CHECK_EQ(2, m.code[0]->OutputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
Node* node = m.NewNode(odpi.op, m.NewNode(shift.op, m.Parameter(0),
|
|
m.Int32Constant(imm)),
|
|
m.Parameter(1));
|
|
m.Return(m.Word32Equal(m.Projection(0, node), m.Projection(1, node)));
|
|
m.SelectInstructions();
|
|
CHECK_LE(1, m.code.size());
|
|
CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kOverflow, m.code[0]->flags_condition());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(2)));
|
|
CHECK_EQ(2, m.code[0]->OutputCount());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32AndAndWord32XorWithMinus1P) {
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(m.Parameter(0),
|
|
m.Word32Xor(m.Int32Constant(-1), m.Parameter(1))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmBic, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(m.Parameter(0),
|
|
m.Word32Xor(m.Parameter(1), m.Int32Constant(-1))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmBic, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(m.Word32Xor(m.Int32Constant(-1), m.Parameter(0)),
|
|
m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmBic, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(m.Word32Xor(m.Parameter(0), m.Int32Constant(-1)),
|
|
m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmBic, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32AndAndWord32XorWithMinus1AndShiftP) {
|
|
Shifts shifts;
|
|
for (Shifts::const_iterator i = shifts.begin(); i != shifts.end(); ++i) {
|
|
Shift shift = *i;
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(
|
|
m.Parameter(0),
|
|
m.Word32Xor(m.Int32Constant(-1),
|
|
m.NewNode(shift.op, m.Parameter(1), m.Parameter(2)))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmBic, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(
|
|
m.Parameter(0),
|
|
m.Word32Xor(m.NewNode(shift.op, m.Parameter(1), m.Parameter(2)),
|
|
m.Int32Constant(-1))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmBic, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(
|
|
m.Word32Xor(m.Int32Constant(-1),
|
|
m.NewNode(shift.op, m.Parameter(0), m.Parameter(1))),
|
|
m.Parameter(2)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmBic, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(
|
|
m.Word32Xor(m.NewNode(shift.op, m.Parameter(0), m.Parameter(1)),
|
|
m.Int32Constant(-1)),
|
|
m.Parameter(2)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmBic, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32XorWithMinus1P) {
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Xor(m.Int32Constant(-1), m.Parameter(0)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMvn, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Xor(m.Parameter(0), m.Int32Constant(-1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMvn, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32XorWithMinus1AndShiftP) {
|
|
Shifts shifts;
|
|
for (Shifts::const_iterator i = shifts.begin(); i != shifts.end(); ++i) {
|
|
Shift shift = *i;
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(
|
|
m.Word32Xor(m.Int32Constant(-1),
|
|
m.NewNode(shift.op, m.Parameter(0), m.Parameter(1))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMvn, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Xor(m.NewNode(shift.op, m.Parameter(0), m.Parameter(1)),
|
|
m.Int32Constant(-1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMvn, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorShiftP) {
|
|
Shifts shifts;
|
|
for (Shifts::const_iterator i = shifts.begin(); i != shifts.end(); ++i) {
|
|
Shift shift = *i;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.NewNode(shift.op, m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMov, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorShiftImm) {
|
|
Shifts shifts;
|
|
for (Shifts::const_iterator i = shifts.begin(); i != shifts.end(); ++i) {
|
|
Shift shift = *i;
|
|
for (int32_t imm = shift.i_low; imm <= shift.i_high; ++imm) {
|
|
InstructionSelectorTester m;
|
|
m.Return(m.NewNode(shift.op, m.Parameter(0), m.Int32Constant(imm)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMov, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorRotateRightP) {
|
|
{
|
|
InstructionSelectorTester m;
|
|
Node* value = m.Parameter(0);
|
|
Node* shift = m.Parameter(1);
|
|
m.Return(
|
|
m.Word32Or(m.Word32Shr(value, shift),
|
|
m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMov, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
Node* value = m.Parameter(0);
|
|
Node* shift = m.Parameter(1);
|
|
m.Return(
|
|
m.Word32Or(m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift)),
|
|
m.Word32Shr(value, shift)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMov, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorRotateRightImm) {
|
|
FOR_INPUTS(uint32_t, ror, i) {
|
|
uint32_t shift = *i;
|
|
{
|
|
InstructionSelectorTester m;
|
|
Node* value = m.Parameter(0);
|
|
m.Return(m.Word32Or(m.Word32Shr(value, m.Int32Constant(shift)),
|
|
m.Word32Shl(value, m.Int32Constant(32 - shift))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMov, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
CHECK_EQ(shift, m.ToInt32(m.code[0]->InputAt(1)));
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
Node* value = m.Parameter(0);
|
|
m.Return(m.Word32Or(m.Word32Shl(value, m.Int32Constant(32 - shift)),
|
|
m.Word32Shr(value, m.Int32Constant(shift))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMov, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
CHECK_EQ(shift, m.ToInt32(m.code[0]->InputAt(1)));
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32MulP) {
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Mul(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMul, m.code[0]->arch_opcode());
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32MulImm) {
|
|
// x * (2^k + 1) -> (x >> k) + x
|
|
for (int k = 1; k < 31; ++k) {
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Mul(m.Parameter(0), m.Int32Constant((1 << k) + 1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmAdd, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_LSL_I, m.code[0]->addressing_mode());
|
|
}
|
|
// (2^k + 1) * x -> (x >> k) + x
|
|
for (int k = 1; k < 31; ++k) {
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Mul(m.Int32Constant((1 << k) + 1), m.Parameter(0)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmAdd, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_LSL_I, m.code[0]->addressing_mode());
|
|
}
|
|
// x * (2^k - 1) -> (x >> k) - x
|
|
for (int k = 3; k < 31; ++k) {
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Mul(m.Parameter(0), m.Int32Constant((1 << k) - 1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmRsb, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_LSL_I, m.code[0]->addressing_mode());
|
|
}
|
|
// (2^k - 1) * x -> (x >> k) - x
|
|
for (int k = 3; k < 31; ++k) {
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Mul(m.Int32Constant((1 << k) - 1), m.Parameter(0)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmRsb, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_LSL_I, m.code[0]->addressing_mode());
|
|
}
|
|
}
|
|
|
|
|
|
// The following tests depend on the exact CPU features available, which we do
|
|
// only fully control in a simulator build.
|
|
#ifdef USE_SIMULATOR
|
|
|
|
TEST(InstructionSelectorDPIImm_ARMv7AndVFP3Disabled) {
|
|
i::FLAG_enable_armv7 = false;
|
|
i::FLAG_enable_vfp3 = false;
|
|
DPIs dpis;
|
|
Immediates immediates;
|
|
for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
|
|
DPI dpi = *i;
|
|
for (Immediates::const_iterator j = immediates.begin();
|
|
j != immediates.end(); ++j) {
|
|
int32_t imm = *j;
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Int32Constant(imm)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.NewNode(dpi.op, m.Int32Constant(imm), m.Parameter(0)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32AndImm_ARMv7Enabled) {
|
|
i::FLAG_enable_armv7 = true;
|
|
for (uint32_t width = 1; width <= 32; ++width) {
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(m.Parameter(0),
|
|
m.Int32Constant(0xffffffffu >> (32 - width))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(0, m.ToInt32(m.code[0]->InputAt(1)));
|
|
CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
for (uint32_t lsb = 0; lsb <= 31; ++lsb) {
|
|
for (uint32_t width = 1; width < 32 - lsb; ++width) {
|
|
uint32_t msk = ~((0xffffffffu >> (32 - width)) << lsb);
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(m.Parameter(0), m.Int32Constant(msk)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmBfc, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK(UnallocatedOperand::cast(m.code[0]->Output())
|
|
->HasSameAsInputPolicy());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
|
|
CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32AndAndWord32ShrImm_ARMv7Enabled) {
|
|
i::FLAG_enable_armv7 = true;
|
|
for (uint32_t lsb = 0; lsb <= 31; ++lsb) {
|
|
for (uint32_t width = 1; width <= 32 - lsb; ++width) {
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb)),
|
|
m.Int32Constant(0xffffffffu >> (32 - width))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
|
|
CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(
|
|
m.Word32And(m.Int32Constant(0xffffffffu >> (32 - width)),
|
|
m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
|
|
CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32ShrAndWord32AndImm_ARMv7Enabled) {
|
|
i::FLAG_enable_armv7 = true;
|
|
for (uint32_t lsb = 0; lsb <= 31; ++lsb) {
|
|
for (uint32_t width = 1; width <= 32 - lsb; ++width) {
|
|
uint32_t max = 1 << lsb;
|
|
if (max > static_cast<uint32_t>(kMaxInt)) max -= 1;
|
|
uint32_t jnk = CcTest::random_number_generator()->NextInt(max);
|
|
uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk;
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Shr(m.Word32And(m.Parameter(0), m.Int32Constant(msk)),
|
|
m.Int32Constant(lsb)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
|
|
CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(msk), m.Parameter(0)),
|
|
m.Int32Constant(lsb)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
|
|
CHECK_EQ(3, m.code[0]->InputCount());
|
|
CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
|
|
CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32SubAndInt32MulP_MlsEnabled) {
|
|
i::FLAG_enable_mls = true;
|
|
InstructionSelectorTester m;
|
|
m.Return(
|
|
m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmMls, m.code[0]->arch_opcode());
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32SubAndInt32MulP_MlsDisabled) {
|
|
i::FLAG_enable_mls = false;
|
|
InstructionSelectorTester m;
|
|
m.Return(
|
|
m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(2, m.code.size());
|
|
CHECK_EQ(kArmMul, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK_EQ(kArmSub, m.code[1]->arch_opcode());
|
|
CHECK_EQ(2, m.code[1]->InputCount());
|
|
CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(1));
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32DivP_ARMv7AndSudivEnabled) {
|
|
i::FLAG_enable_armv7 = true;
|
|
i::FLAG_enable_sudiv = true;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32DivP_SudivDisabled) {
|
|
i::FLAG_enable_sudiv = false;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(4, m.code.size());
|
|
CHECK_EQ(kArmVcvtF64S32, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK_EQ(kArmVcvtF64S32, m.code[1]->arch_opcode());
|
|
CHECK_EQ(1, m.code[1]->OutputCount());
|
|
CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode());
|
|
CHECK_EQ(2, m.code[2]->InputCount());
|
|
CHECK_EQ(1, m.code[2]->OutputCount());
|
|
CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0));
|
|
CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
|
|
CHECK_EQ(kArmVcvtS32F64, m.code[3]->arch_opcode());
|
|
CHECK_EQ(1, m.code[3]->InputCount());
|
|
CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0));
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32UDivP_ARMv7AndSudivEnabled) {
|
|
i::FLAG_enable_armv7 = true;
|
|
i::FLAG_enable_sudiv = true;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32UDivP_SudivDisabled) {
|
|
i::FLAG_enable_sudiv = false;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(4, m.code.size());
|
|
CHECK_EQ(kArmVcvtF64U32, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK_EQ(kArmVcvtF64U32, m.code[1]->arch_opcode());
|
|
CHECK_EQ(1, m.code[1]->OutputCount());
|
|
CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode());
|
|
CHECK_EQ(2, m.code[2]->InputCount());
|
|
CHECK_EQ(1, m.code[2]->OutputCount());
|
|
CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0));
|
|
CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
|
|
CHECK_EQ(kArmVcvtU32F64, m.code[3]->arch_opcode());
|
|
CHECK_EQ(1, m.code[3]->InputCount());
|
|
CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0));
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32ModP_ARMv7AndMlsAndSudivEnabled) {
|
|
i::FLAG_enable_armv7 = true;
|
|
i::FLAG_enable_mls = true;
|
|
i::FLAG_enable_sudiv = true;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(2, m.code.size());
|
|
CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
|
|
CHECK_EQ(1, m.code[1]->OutputCount());
|
|
CHECK_EQ(3, m.code[1]->InputCount());
|
|
CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
|
|
CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
|
|
CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32ModP_ARMv7AndSudivEnabled) {
|
|
i::FLAG_enable_armv7 = true;
|
|
i::FLAG_enable_mls = false;
|
|
i::FLAG_enable_sudiv = true;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(3, m.code.size());
|
|
CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
CHECK_EQ(kArmMul, m.code[1]->arch_opcode());
|
|
CHECK_EQ(1, m.code[1]->OutputCount());
|
|
CHECK_EQ(2, m.code[1]->InputCount());
|
|
CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
|
|
CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
|
|
CHECK_EQ(kArmSub, m.code[2]->arch_opcode());
|
|
CHECK_EQ(1, m.code[2]->OutputCount());
|
|
CHECK_EQ(2, m.code[2]->InputCount());
|
|
CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0));
|
|
CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32ModP_ARMv7AndMlsAndSudivDisabled) {
|
|
i::FLAG_enable_armv7 = false;
|
|
i::FLAG_enable_mls = false;
|
|
i::FLAG_enable_sudiv = false;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(6, m.code.size());
|
|
CHECK_EQ(kArmVcvtF64S32, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK_EQ(kArmVcvtF64S32, m.code[1]->arch_opcode());
|
|
CHECK_EQ(1, m.code[1]->OutputCount());
|
|
CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode());
|
|
CHECK_EQ(2, m.code[2]->InputCount());
|
|
CHECK_EQ(1, m.code[2]->OutputCount());
|
|
CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0));
|
|
CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
|
|
CHECK_EQ(kArmVcvtS32F64, m.code[3]->arch_opcode());
|
|
CHECK_EQ(1, m.code[3]->InputCount());
|
|
CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0));
|
|
CHECK_EQ(kArmMul, m.code[4]->arch_opcode());
|
|
CHECK_EQ(1, m.code[4]->OutputCount());
|
|
CHECK_EQ(2, m.code[4]->InputCount());
|
|
CheckSameVreg(m.code[3]->Output(), m.code[4]->InputAt(0));
|
|
CheckSameVreg(m.code[1]->InputAt(0), m.code[4]->InputAt(1));
|
|
CHECK_EQ(kArmSub, m.code[5]->arch_opcode());
|
|
CHECK_EQ(1, m.code[5]->OutputCount());
|
|
CHECK_EQ(2, m.code[5]->InputCount());
|
|
CheckSameVreg(m.code[0]->InputAt(0), m.code[5]->InputAt(0));
|
|
CheckSameVreg(m.code[4]->Output(), m.code[5]->InputAt(1));
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32UModP_ARMv7AndMlsAndSudivEnabled) {
|
|
i::FLAG_enable_armv7 = true;
|
|
i::FLAG_enable_mls = true;
|
|
i::FLAG_enable_sudiv = true;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(2, m.code.size());
|
|
CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
|
|
CHECK_EQ(1, m.code[1]->OutputCount());
|
|
CHECK_EQ(3, m.code[1]->InputCount());
|
|
CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
|
|
CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
|
|
CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32UModP_ARMv7AndSudivEnabled) {
|
|
i::FLAG_enable_armv7 = true;
|
|
i::FLAG_enable_mls = false;
|
|
i::FLAG_enable_sudiv = true;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(3, m.code.size());
|
|
CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
CHECK_EQ(kArmMul, m.code[1]->arch_opcode());
|
|
CHECK_EQ(1, m.code[1]->OutputCount());
|
|
CHECK_EQ(2, m.code[1]->InputCount());
|
|
CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
|
|
CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
|
|
CHECK_EQ(kArmSub, m.code[2]->arch_opcode());
|
|
CHECK_EQ(1, m.code[2]->OutputCount());
|
|
CHECK_EQ(2, m.code[2]->InputCount());
|
|
CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0));
|
|
CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorInt32UModP_ARMv7AndMlsAndSudivDisabled) {
|
|
i::FLAG_enable_armv7 = false;
|
|
i::FLAG_enable_mls = false;
|
|
i::FLAG_enable_sudiv = false;
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(6, m.code.size());
|
|
CHECK_EQ(kArmVcvtF64U32, m.code[0]->arch_opcode());
|
|
CHECK_EQ(1, m.code[0]->OutputCount());
|
|
CHECK_EQ(kArmVcvtF64U32, m.code[1]->arch_opcode());
|
|
CHECK_EQ(1, m.code[1]->OutputCount());
|
|
CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode());
|
|
CHECK_EQ(2, m.code[2]->InputCount());
|
|
CHECK_EQ(1, m.code[2]->OutputCount());
|
|
CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0));
|
|
CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
|
|
CHECK_EQ(kArmVcvtU32F64, m.code[3]->arch_opcode());
|
|
CHECK_EQ(1, m.code[3]->InputCount());
|
|
CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0));
|
|
CHECK_EQ(kArmMul, m.code[4]->arch_opcode());
|
|
CHECK_EQ(1, m.code[4]->OutputCount());
|
|
CHECK_EQ(2, m.code[4]->InputCount());
|
|
CheckSameVreg(m.code[3]->Output(), m.code[4]->InputAt(0));
|
|
CheckSameVreg(m.code[1]->InputAt(0), m.code[4]->InputAt(1));
|
|
CHECK_EQ(kArmSub, m.code[5]->arch_opcode());
|
|
CHECK_EQ(1, m.code[5]->OutputCount());
|
|
CHECK_EQ(2, m.code[5]->InputCount());
|
|
CheckSameVreg(m.code[0]->InputAt(0), m.code[5]->InputAt(0));
|
|
CheckSameVreg(m.code[4]->Output(), m.code[5]->InputAt(1));
|
|
}
|
|
|
|
#endif // USE_SIMULATOR
|
|
|
|
|
|
TEST(InstructionSelectorWord32EqualP) {
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(m.Parameter(0), m.Parameter(1)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32EqualImm) {
|
|
Immediates immediates;
|
|
for (Immediates::const_iterator i = immediates.begin(); i != immediates.end();
|
|
++i) {
|
|
int32_t imm = *i;
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(m.Parameter(0), m.Int32Constant(imm)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
if (imm == 0) {
|
|
CHECK_EQ(kArmTst, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
CheckSameVreg(m.code[0]->InputAt(0), m.code[0]->InputAt(1));
|
|
} else {
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
|
|
}
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(m.Int32Constant(imm), m.Parameter(0)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
if (imm == 0) {
|
|
CHECK_EQ(kArmTst, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(2, m.code[0]->InputCount());
|
|
CheckSameVreg(m.code[0]->InputAt(0), m.code[0]->InputAt(1));
|
|
} else {
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
|
|
}
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32EqualAndDPIP) {
|
|
DPIs dpis;
|
|
for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
|
|
DPI dpi = *i;
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(m.NewNode(dpi.op, m.Parameter(0), m.Parameter(1)),
|
|
m.Int32Constant(0)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.test_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(
|
|
m.Word32Equal(m.Int32Constant(0),
|
|
m.NewNode(dpi.op, m.Parameter(0), m.Parameter(1))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.test_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32EqualAndDPIImm) {
|
|
DPIs dpis;
|
|
Immediates immediates;
|
|
for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
|
|
DPI dpi = *i;
|
|
for (Immediates::const_iterator j = immediates.begin();
|
|
j != immediates.end(); ++j) {
|
|
int32_t imm = *j;
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(
|
|
m.NewNode(dpi.op, m.Parameter(0), m.Int32Constant(imm)),
|
|
m.Int32Constant(0)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.test_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(
|
|
m.NewNode(dpi.op, m.Int32Constant(imm), m.Parameter(0)),
|
|
m.Int32Constant(0)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.test_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(
|
|
m.Int32Constant(0),
|
|
m.NewNode(dpi.op, m.Parameter(0), m.Int32Constant(imm))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.test_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(
|
|
m.Int32Constant(0),
|
|
m.NewNode(dpi.op, m.Int32Constant(imm), m.Parameter(0))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.test_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorWord32EqualAndShiftP) {
|
|
Shifts shifts;
|
|
for (Shifts::const_iterator i = shifts.begin(); i != shifts.end(); ++i) {
|
|
Shift shift = *i;
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(
|
|
m.Parameter(0), m.NewNode(shift.op, m.Parameter(1), m.Parameter(2))));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
m.Return(m.Word32Equal(
|
|
m.NewNode(shift.op, m.Parameter(0), m.Parameter(1)), m.Parameter(2)));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorBranchWithWord32EqualAndShiftP) {
|
|
Shifts shifts;
|
|
for (Shifts::const_iterator i = shifts.begin(); i != shifts.end(); ++i) {
|
|
Shift shift = *i;
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
m.Branch(m.Word32Equal(m.Parameter(0), m.NewNode(shift.op, m.Parameter(1),
|
|
m.Parameter(2))),
|
|
&blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
m.Branch(
|
|
m.Word32Equal(m.NewNode(shift.op, m.Parameter(1), m.Parameter(2)),
|
|
m.Parameter(0)),
|
|
&blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.r_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorBranchWithWord32EqualAndShiftImm) {
|
|
Shifts shifts;
|
|
for (Shifts::const_iterator i = shifts.begin(); i != shifts.end(); ++i) {
|
|
Shift shift = *i;
|
|
for (int32_t imm = shift.i_low; imm <= shift.i_high; ++imm) {
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
m.Branch(
|
|
m.Word32Equal(m.Parameter(0), m.NewNode(shift.op, m.Parameter(1),
|
|
m.Int32Constant(imm))),
|
|
&blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
m.Branch(m.Word32Equal(
|
|
m.NewNode(shift.op, m.Parameter(1), m.Int32Constant(imm)),
|
|
m.Parameter(0)),
|
|
&blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(shift.i_mode, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorBranchWithWord32EqualAndRotateRightP) {
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
Node* input = m.Parameter(0);
|
|
Node* value = m.Parameter(1);
|
|
Node* shift = m.Parameter(2);
|
|
Node* ror =
|
|
m.Word32Or(m.Word32Shr(value, shift),
|
|
m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift)));
|
|
m.Branch(m.Word32Equal(input, ror), &blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
Node* input = m.Parameter(0);
|
|
Node* value = m.Parameter(1);
|
|
Node* shift = m.Parameter(2);
|
|
Node* ror =
|
|
m.Word32Or(m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift)),
|
|
m.Word32Shr(value, shift));
|
|
m.Branch(m.Word32Equal(input, ror), &blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
Node* input = m.Parameter(0);
|
|
Node* value = m.Parameter(1);
|
|
Node* shift = m.Parameter(2);
|
|
Node* ror =
|
|
m.Word32Or(m.Word32Shr(value, shift),
|
|
m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift)));
|
|
m.Branch(m.Word32Equal(ror, input), &blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
Node* input = m.Parameter(0);
|
|
Node* value = m.Parameter(1);
|
|
Node* shift = m.Parameter(2);
|
|
Node* ror =
|
|
m.Word32Or(m.Word32Shl(value, m.Int32Sub(m.Int32Constant(32), shift)),
|
|
m.Word32Shr(value, shift));
|
|
m.Branch(m.Word32Equal(ror, input), &blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorBranchWithWord32EqualAndRotateRightImm) {
|
|
FOR_INPUTS(uint32_t, ror, i) {
|
|
uint32_t shift = *i;
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
Node* input = m.Parameter(0);
|
|
Node* value = m.Parameter(1);
|
|
Node* ror = m.Word32Or(m.Word32Shr(value, m.Int32Constant(shift)),
|
|
m.Word32Shl(value, m.Int32Constant(32 - shift)));
|
|
m.Branch(m.Word32Equal(input, ror), &blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
CHECK_LE(3, m.code[0]->InputCount());
|
|
CHECK_EQ(shift, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
Node* input = m.Parameter(0);
|
|
Node* value = m.Parameter(1);
|
|
Node* ror = m.Word32Or(m.Word32Shl(value, m.Int32Constant(32 - shift)),
|
|
m.Word32Shr(value, m.Int32Constant(shift)));
|
|
m.Branch(m.Word32Equal(input, ror), &blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
CHECK_LE(3, m.code[0]->InputCount());
|
|
CHECK_EQ(shift, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
Node* input = m.Parameter(0);
|
|
Node* value = m.Parameter(1);
|
|
Node* ror = m.Word32Or(m.Word32Shr(value, m.Int32Constant(shift)),
|
|
m.Word32Shl(value, m.Int32Constant(32 - shift)));
|
|
m.Branch(m.Word32Equal(ror, input), &blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
CHECK_LE(3, m.code[0]->InputCount());
|
|
CHECK_EQ(shift, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
Node* input = m.Parameter(0);
|
|
Node* value = m.Parameter(1);
|
|
Node* ror = m.Word32Or(m.Word32Shl(value, m.Int32Constant(32 - shift)),
|
|
m.Word32Shr(value, m.Int32Constant(shift)));
|
|
m.Branch(m.Word32Equal(ror, input), &blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R_ROR_I, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
CHECK_LE(3, m.code[0]->InputCount());
|
|
CHECK_EQ(shift, m.ToInt32(m.code[0]->InputAt(2)));
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST(InstructionSelectorBranchWithDPIP) {
|
|
DPIs dpis;
|
|
for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
|
|
DPI dpi = *i;
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
m.Branch(m.NewNode(dpi.op, m.Parameter(0), m.Parameter(1)), &blocka,
|
|
&blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.test_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kNotEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
m.Branch(m.Word32Equal(m.Int32Constant(0),
|
|
m.NewNode(dpi.op, m.Parameter(0), m.Parameter(1))),
|
|
&blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.test_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
{
|
|
InstructionSelectorTester m;
|
|
MLabel blocka, blockb;
|
|
m.Branch(m.Word32Equal(m.NewNode(dpi.op, m.Parameter(0), m.Parameter(1)),
|
|
m.Int32Constant(0)),
|
|
&blocka, &blockb);
|
|
m.Bind(&blocka);
|
|
m.Return(m.Int32Constant(1));
|
|
m.Bind(&blockb);
|
|
m.Return(m.Int32Constant(0));
|
|
m.SelectInstructions();
|
|
CHECK_EQ(1, m.code.size());
|
|
CHECK_EQ(dpi.test_arch_opcode, m.code[0]->arch_opcode());
|
|
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
|
|
CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
|
|
CHECK_EQ(kEqual, m.code[0]->flags_condition());
|
|
}
|
|
}
|
|
}
|