4d18959446
(at the moment only if we do not need to allocate a heap number). Find a few more oportunities to avoid heap number allocation on IA32. Add some infrastructure to test coverage of generated ARM code in our tests. Review URL: http://codereview.chromium.org/67163 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@1720 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
205 lines
7.2 KiB
C++
205 lines
7.2 KiB
C++
// Copyright 2008 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Declares a Simulator for ARM instructions if we are not generating a native
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// ARM binary. This Simulator allows us to run and debug ARM code generation on
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// regular desktop machines.
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// V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro,
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// which will start execution in the Simulator or forwards to the real entry
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// on a ARM HW platform.
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#ifndef V8_SIMULATOR_ARM_H_
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#define V8_SIMULATOR_ARM_H_
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#if defined(__arm__)
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// When running without a simulator we call the entry directly.
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#define CALL_GENERATED_CODE(entry, p0, p1, p2, p3, p4) \
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entry(p0, p1, p2, p3, p4)
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// Calculated the stack limit beyond which we will throw stack overflow errors.
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// This macro must be called from a C++ method. It relies on being able to take
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// the address of "this" to get a value on the current execution stack and then
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// calculates the stack limit based on that value.
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#define GENERATED_CODE_STACK_LIMIT(limit) \
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(reinterpret_cast<uintptr_t>(this) - limit)
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#else // defined(__arm__)
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// When running with the simulator transition into simulated execution at this
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// point.
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#define CALL_GENERATED_CODE(entry, p0, p1, p2, p3, p4) \
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assembler::arm::Simulator::current()->Call((int32_t)entry, (int32_t)p0, \
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(int32_t)p1, (int32_t)p2, (int32_t)p3, (int32_t)p4)
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// The simulator has its own stack. Thus it has a different stack limit from
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// the C-based native code.
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#define GENERATED_CODE_STACK_LIMIT(limit) \
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(assembler::arm::Simulator::current()->StackLimit())
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#include "constants-arm.h"
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namespace assembler { namespace arm {
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class Simulator {
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public:
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friend class Debugger;
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enum Register {
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no_reg = -1,
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r0 = 0, r1, r2, r3, r4, r5, r6, r7,
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r8, r9, r10, r11, r12, r13, r14, r15,
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num_registers,
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sp = 13,
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lr = 14,
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pc = 15
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};
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Simulator();
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~Simulator();
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// The currently executing Simulator instance. Potentially there can be one
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// for each native thread.
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static Simulator* current();
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// Accessors for register state. Reading the pc value adheres to the ARM
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// architecture specification and is off by a 8 from the currently executing
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// instruction.
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void set_register(int reg, int32_t value);
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int32_t get_register(int reg) const;
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// Special case of set_register and get_register to access the raw PC value.
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void set_pc(int32_t value);
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int32_t get_pc() const;
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// Accessor to the internal simulator stack area.
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uintptr_t StackLimit() const;
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// Executes ARM instructions until the PC reaches end_sim_pc.
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void Execute();
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// V8 generally calls into generated code with 5 parameters. This is a
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// convenience function, which sets up the simulator state and grabs the
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// result on return.
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v8::internal::Object* Call(int32_t entry, int32_t p0, int32_t p1,
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int32_t p2, int32_t p3, int32_t p4);
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private:
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enum special_values {
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// Known bad pc value to ensure that the simulator does not execute
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// without being properly setup.
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bad_lr = -1,
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// A pc value used to signal the simulator to stop execution. Generally
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// the lr is set to this value on transition from native C code to
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// simulated execution, so that the simulator can "return" to the native
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// C code.
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end_sim_pc = -2
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};
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// Unsupported instructions use Format to print an error and stop execution.
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void Format(Instr* instr, const char* format);
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// Checks if the current instruction should be executed based on its
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// condition bits.
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bool ConditionallyExecute(Instr* instr);
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// Helper functions to set the conditional flags in the architecture state.
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void SetNZFlags(int32_t val);
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void SetCFlag(bool val);
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void SetVFlag(bool val);
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bool CarryFrom(int32_t left, int32_t right);
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bool BorrowFrom(int32_t left, int32_t right);
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bool OverflowFrom(int32_t alu_out,
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int32_t left,
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int32_t right,
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bool addition);
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// Helper functions to decode common "addressing" modes
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int32_t GetShiftRm(Instr* instr, bool* carry_out);
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int32_t GetImm(Instr* instr, bool* carry_out);
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void HandleRList(Instr* instr, bool load);
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void SoftwareInterrupt(Instr* instr);
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// Read and write memory.
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inline uint8_t ReadBU(int32_t addr);
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inline int8_t ReadB(int32_t addr);
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inline void WriteB(int32_t addr, uint8_t value);
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inline void WriteB(int32_t addr, int8_t value);
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inline uint16_t ReadHU(int32_t addr, Instr* instr);
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inline int16_t ReadH(int32_t addr, Instr* instr);
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// Note: Overloaded on the sign of the value.
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inline void WriteH(int32_t addr, uint16_t value, Instr* instr);
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inline void WriteH(int32_t addr, int16_t value, Instr* instr);
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inline int ReadW(int32_t addr, Instr* instr);
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inline void WriteW(int32_t addr, int value, Instr* instr);
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// Executing is handled based on the instruction type.
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void DecodeType01(Instr* instr); // both type 0 and type 1 rolled into one
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void DecodeType2(Instr* instr);
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void DecodeType3(Instr* instr);
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void DecodeType4(Instr* instr);
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void DecodeType5(Instr* instr);
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void DecodeType6(Instr* instr);
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void DecodeType7(Instr* instr);
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// Executes one instruction.
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void InstructionDecode(Instr* instr);
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// For use in calls that take two double values, constructed from r0, r1, r2
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// and r3.
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void GetFpArgs(double* x, double* y);
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void SetFpResult(const double& result);
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void TrashCallerSaveRegisters();
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// architecture state
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int32_t registers_[16];
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bool n_flag_;
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bool z_flag_;
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bool c_flag_;
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bool v_flag_;
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// simulator support
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char* stack_;
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bool pc_modified_;
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int icount_;
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// registered breakpoints
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Instr* break_pc_;
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instr_t break_instr_;
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};
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} } // namespace assembler::arm
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#endif // defined(__arm__)
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#endif // V8_SIMULATOR_ARM_H_
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