e61bd7bd26
Upgraded the CodeGenerator::ToBoolean() function in the ARM backend to use complete JIT code generation and not make runtime calls to ToBool (when VFP is enabled). This change also includes the vcmp VFP instruction that supports a constant 0.0 as the second operand. Patch by Subrato K De <subratokde@codeaurora.org> git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5267 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
1466 lines
43 KiB
C++
1466 lines
43 KiB
C++
// Copyright 2010 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// A Disassembler object is used to disassemble a block of code instruction by
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// instruction. The default implementation of the NameConverter object can be
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// overriden to modify register names or to do symbol lookup on addresses.
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//
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// The example below will disassemble a block of code and print it to stdout.
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//
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// NameConverter converter;
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// Disassembler d(converter);
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// for (byte* pc = begin; pc < end;) {
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// v8::internal::EmbeddedVector<char, 256> buffer;
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// byte* prev_pc = pc;
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// pc += d.InstructionDecode(buffer, pc);
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// printf("%p %08x %s\n",
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// prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer);
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// }
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//
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// The Disassembler class also has a convenience method to disassemble a block
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// of code into a FILE*, meaning that the above functionality could also be
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// achieved by just calling Disassembler::Disassemble(stdout, begin, end);
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#include <assert.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#ifndef WIN32
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#include <stdint.h>
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#endif
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#include "v8.h"
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#if defined(V8_TARGET_ARCH_ARM)
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#include "constants-arm.h"
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#include "disasm.h"
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#include "macro-assembler.h"
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#include "platform.h"
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namespace assembler {
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namespace arm {
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namespace v8i = v8::internal;
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//------------------------------------------------------------------------------
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// Decoder decodes and disassembles instructions into an output buffer.
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// It uses the converter to convert register names and call destinations into
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// more informative description.
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class Decoder {
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public:
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Decoder(const disasm::NameConverter& converter,
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v8::internal::Vector<char> out_buffer)
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: converter_(converter),
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out_buffer_(out_buffer),
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out_buffer_pos_(0) {
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out_buffer_[out_buffer_pos_] = '\0';
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}
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~Decoder() {}
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// Writes one disassembled instruction into 'buffer' (0-terminated).
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// Returns the length of the disassembled machine instruction in bytes.
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int InstructionDecode(byte* instruction);
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private:
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// Bottleneck functions to print into the out_buffer.
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void PrintChar(const char ch);
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void Print(const char* str);
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// Printing of common values.
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void PrintRegister(int reg);
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void PrintSRegister(int reg);
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void PrintDRegister(int reg);
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int FormatVFPRegister(Instr* instr, const char* format);
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void PrintMovwMovt(Instr* instr);
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int FormatVFPinstruction(Instr* instr, const char* format);
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void PrintCondition(Instr* instr);
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void PrintShiftRm(Instr* instr);
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void PrintShiftImm(Instr* instr);
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void PrintShiftSat(Instr* instr);
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void PrintPU(Instr* instr);
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void PrintSoftwareInterrupt(SoftwareInterruptCodes swi);
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// Handle formatting of instructions and their options.
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int FormatRegister(Instr* instr, const char* option);
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int FormatOption(Instr* instr, const char* option);
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void Format(Instr* instr, const char* format);
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void Unknown(Instr* instr);
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// Each of these functions decodes one particular instruction type, a 3-bit
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// field in the instruction encoding.
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// Types 0 and 1 are combined as they are largely the same except for the way
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// they interpret the shifter operand.
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void DecodeType01(Instr* instr);
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void DecodeType2(Instr* instr);
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void DecodeType3(Instr* instr);
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void DecodeType4(Instr* instr);
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void DecodeType5(Instr* instr);
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void DecodeType6(Instr* instr);
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void DecodeType7(Instr* instr);
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void DecodeUnconditional(Instr* instr);
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// For VFP support.
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void DecodeTypeVFP(Instr* instr);
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void DecodeType6CoprocessorIns(Instr* instr);
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void DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr);
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void DecodeVCMP(Instr* instr);
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void DecodeVCVTBetweenDoubleAndSingle(Instr* instr);
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void DecodeVCVTBetweenFloatingPointAndInteger(Instr* instr);
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const disasm::NameConverter& converter_;
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v8::internal::Vector<char> out_buffer_;
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int out_buffer_pos_;
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DISALLOW_COPY_AND_ASSIGN(Decoder);
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};
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// Support for assertions in the Decoder formatting functions.
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#define STRING_STARTS_WITH(string, compare_string) \
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(strncmp(string, compare_string, strlen(compare_string)) == 0)
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// Append the ch to the output buffer.
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void Decoder::PrintChar(const char ch) {
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out_buffer_[out_buffer_pos_++] = ch;
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}
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// Append the str to the output buffer.
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void Decoder::Print(const char* str) {
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char cur = *str++;
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while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
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PrintChar(cur);
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cur = *str++;
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}
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out_buffer_[out_buffer_pos_] = 0;
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}
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// These condition names are defined in a way to match the native disassembler
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// formatting. See for example the command "objdump -d <binary file>".
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static const char* cond_names[max_condition] = {
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"eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" ,
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"hi", "ls", "ge", "lt", "gt", "le", "", "invalid",
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};
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// Print the condition guarding the instruction.
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void Decoder::PrintCondition(Instr* instr) {
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Print(cond_names[instr->ConditionField()]);
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}
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// Print the register name according to the active name converter.
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void Decoder::PrintRegister(int reg) {
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Print(converter_.NameOfCPURegister(reg));
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}
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// Print the VFP S register name according to the active name converter.
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void Decoder::PrintSRegister(int reg) {
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Print(assembler::arm::VFPRegisters::Name(reg, false));
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}
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// Print the VFP D register name according to the active name converter.
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void Decoder::PrintDRegister(int reg) {
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Print(assembler::arm::VFPRegisters::Name(reg, true));
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}
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// These shift names are defined in a way to match the native disassembler
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// formatting. See for example the command "objdump -d <binary file>".
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static const char* shift_names[max_shift] = {
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"lsl", "lsr", "asr", "ror"
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};
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// Print the register shift operands for the instruction. Generally used for
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// data processing instructions.
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void Decoder::PrintShiftRm(Instr* instr) {
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Shift shift = instr->ShiftField();
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int shift_amount = instr->ShiftAmountField();
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int rm = instr->RmField();
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PrintRegister(rm);
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if ((instr->RegShiftField() == 0) && (shift == LSL) && (shift_amount == 0)) {
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// Special case for using rm only.
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return;
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}
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if (instr->RegShiftField() == 0) {
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// by immediate
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if ((shift == ROR) && (shift_amount == 0)) {
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Print(", RRX");
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return;
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} else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
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shift_amount = 32;
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}
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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", %s #%d",
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shift_names[shift], shift_amount);
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} else {
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// by register
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int rs = instr->RsField();
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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", %s ", shift_names[shift]);
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PrintRegister(rs);
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}
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}
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// Print the immediate operand for the instruction. Generally used for data
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// processing instructions.
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void Decoder::PrintShiftImm(Instr* instr) {
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int rotate = instr->RotateField() * 2;
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int immed8 = instr->Immed8Field();
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int imm = (immed8 >> rotate) | (immed8 << (32 - rotate));
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"#%d", imm);
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}
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// Print the optional shift and immediate used by saturating instructions.
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void Decoder::PrintShiftSat(Instr* instr) {
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int shift = instr->Bits(11, 7);
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if (shift > 0) {
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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", %s #%d",
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shift_names[instr->Bit(6) * 2],
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instr->Bits(11, 7));
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}
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}
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// Print PU formatting to reduce complexity of FormatOption.
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void Decoder::PrintPU(Instr* instr) {
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switch (instr->PUField()) {
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case 0: {
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Print("da");
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break;
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}
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case 1: {
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Print("ia");
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break;
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}
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case 2: {
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Print("db");
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break;
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}
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case 3: {
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Print("ib");
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break;
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}
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default: {
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UNREACHABLE();
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break;
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}
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}
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}
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// Print SoftwareInterrupt codes. Factoring this out reduces the complexity of
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// the FormatOption method.
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void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes swi) {
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switch (swi) {
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case call_rt_redirected:
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Print("call_rt_redirected");
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return;
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case break_point:
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Print("break_point");
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return;
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default:
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"%d",
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swi);
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return;
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}
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}
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// Handle all register based formatting in this function to reduce the
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// complexity of FormatOption.
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int Decoder::FormatRegister(Instr* instr, const char* format) {
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ASSERT(format[0] == 'r');
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if (format[1] == 'n') { // 'rn: Rn register
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int reg = instr->RnField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'd') { // 'rd: Rd register
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int reg = instr->RdField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 's') { // 'rs: Rs register
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int reg = instr->RsField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'm') { // 'rm: Rm register
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int reg = instr->RmField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 't') { // 'rt: Rt register
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int reg = instr->RtField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'l') {
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// 'rlist: register list for load and store multiple instructions
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ASSERT(STRING_STARTS_WITH(format, "rlist"));
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int rlist = instr->RlistField();
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int reg = 0;
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Print("{");
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// Print register list in ascending order, by scanning the bit mask.
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while (rlist != 0) {
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if ((rlist & 1) != 0) {
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PrintRegister(reg);
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if ((rlist >> 1) != 0) {
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Print(", ");
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}
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}
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reg++;
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rlist >>= 1;
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}
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Print("}");
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return 5;
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}
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UNREACHABLE();
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return -1;
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}
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// Handle all VFP register based formatting in this function to reduce the
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// complexity of FormatOption.
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int Decoder::FormatVFPRegister(Instr* instr, const char* format) {
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ASSERT((format[0] == 'S') || (format[0] == 'D'));
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if (format[1] == 'n') {
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int reg = instr->VnField();
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if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->NField()));
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if (format[0] == 'D') PrintDRegister(reg);
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return 2;
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} else if (format[1] == 'm') {
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int reg = instr->VmField();
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if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->MField()));
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if (format[0] == 'D') PrintDRegister(reg);
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return 2;
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} else if (format[1] == 'd') {
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int reg = instr->VdField();
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if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->DField()));
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if (format[0] == 'D') PrintDRegister(reg);
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return 2;
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}
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UNREACHABLE();
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return -1;
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}
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int Decoder::FormatVFPinstruction(Instr* instr, const char* format) {
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Print(format);
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return 0;
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}
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// Print the movw or movt instruction.
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void Decoder::PrintMovwMovt(Instr* instr) {
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int imm = instr->ImmedMovwMovtField();
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int rd = instr->RdField();
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PrintRegister(rd);
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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", #%d", imm);
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}
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// FormatOption takes a formatting string and interprets it based on
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// the current instructions. The format string points to the first
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// character of the option string (the option escape has already been
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// consumed by the caller.) FormatOption returns the number of
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// characters that were consumed from the formatting string.
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int Decoder::FormatOption(Instr* instr, const char* format) {
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switch (format[0]) {
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case 'a': { // 'a: accumulate multiplies
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if (instr->Bit(21) == 0) {
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Print("ul");
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} else {
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Print("la");
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}
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return 1;
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}
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case 'b': { // 'b: byte loads or stores
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if (instr->HasB()) {
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Print("b");
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}
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return 1;
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}
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case 'c': { // 'cond: conditional execution
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ASSERT(STRING_STARTS_WITH(format, "cond"));
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PrintCondition(instr);
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return 4;
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}
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case 'd': { // 'd: vmov double immediate.
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double d = instr->DoubleImmedVmov();
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"#%g", d);
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return 1;
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}
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case 'f': { // 'f: bitfield instructions - v7 and above.
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uint32_t lsbit = instr->Bits(11, 7);
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uint32_t width = instr->Bits(20, 16) + 1;
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if (instr->Bit(21) == 0) {
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// BFC/BFI:
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// Bits 20-16 represent most-significant bit. Covert to width.
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width -= lsbit;
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ASSERT(width > 0);
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}
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ASSERT((width + lsbit) <= 32);
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"#%d, #%d", lsbit, width);
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return 1;
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}
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case 'h': { // 'h: halfword operation for extra loads and stores
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if (instr->HasH()) {
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Print("h");
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} else {
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Print("b");
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}
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return 1;
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}
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case 'i': { // 'i: immediate value from adjacent bits.
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// Expects tokens in the form imm%02d@%02d, ie. imm05@07, imm10@16
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int width = (format[3] - '0') * 10 + (format[4] - '0');
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int lsb = (format[6] - '0') * 10 + (format[7] - '0');
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ASSERT((width >= 1) && (width <= 32));
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ASSERT((lsb >= 0) && (lsb <= 31));
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ASSERT((width + lsb) <= 32);
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"#%d",
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instr->Bits(width + lsb - 1, lsb));
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return 8;
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}
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case 'l': { // 'l: branch and link
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if (instr->HasLink()) {
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Print("l");
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}
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return 1;
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}
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case 'm': {
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if (format[1] == 'w') {
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// 'mw: movt/movw instructions.
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PrintMovwMovt(instr);
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return 2;
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}
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if (format[1] == 'e') { // 'memop: load/store instructions.
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ASSERT(STRING_STARTS_WITH(format, "memop"));
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if (instr->HasL()) {
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Print("ldr");
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} else if ((instr->Bits(27, 25) == 0) && (instr->Bit(20) == 0)) {
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if (instr->Bits(7, 4) == 0xf) {
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Print("strd");
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} else {
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Print("ldrd");
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}
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} else {
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Print("str");
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}
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return 5;
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}
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// 'msg: for simulator break instructions
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ASSERT(STRING_STARTS_WITH(format, "msg"));
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byte* str =
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reinterpret_cast<byte*>(instr->InstructionBits() & 0x0fffffff);
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out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
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"%s", converter_.NameInCode(str));
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return 3;
|
|
}
|
|
case 'o': {
|
|
if ((format[3] == '1') && (format[4] == '2')) {
|
|
// 'off12: 12-bit offset for load and store instructions
|
|
ASSERT(STRING_STARTS_WITH(format, "off12"));
|
|
out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
|
|
"%d", instr->Offset12Field());
|
|
return 5;
|
|
} else if (format[3] == '0') {
|
|
// 'off0to3and8to19 16-bit immediate encoded in bits 19-8 and 3-0.
|
|
ASSERT(STRING_STARTS_WITH(format, "off0to3and8to19"));
|
|
out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
|
|
"%d",
|
|
(instr->Bits(19, 8) << 4) +
|
|
instr->Bits(3, 0));
|
|
return 15;
|
|
}
|
|
// 'off8: 8-bit offset for extra load and store instructions
|
|
ASSERT(STRING_STARTS_WITH(format, "off8"));
|
|
int offs8 = (instr->ImmedHField() << 4) | instr->ImmedLField();
|
|
out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
|
|
"%d", offs8);
|
|
return 4;
|
|
}
|
|
case 'p': { // 'pu: P and U bits for load and store instructions
|
|
ASSERT(STRING_STARTS_WITH(format, "pu"));
|
|
PrintPU(instr);
|
|
return 2;
|
|
}
|
|
case 'r': {
|
|
return FormatRegister(instr, format);
|
|
}
|
|
case 's': {
|
|
if (format[1] == 'h') { // 'shift_op or 'shift_rm or 'shift_sat.
|
|
if (format[6] == 'o') { // 'shift_op
|
|
ASSERT(STRING_STARTS_WITH(format, "shift_op"));
|
|
if (instr->TypeField() == 0) {
|
|
PrintShiftRm(instr);
|
|
} else {
|
|
ASSERT(instr->TypeField() == 1);
|
|
PrintShiftImm(instr);
|
|
}
|
|
return 8;
|
|
} else if (format[6] == 's') { // 'shift_sat.
|
|
ASSERT(STRING_STARTS_WITH(format, "shift_sat"));
|
|
PrintShiftSat(instr);
|
|
return 9;
|
|
} else { // 'shift_rm
|
|
ASSERT(STRING_STARTS_WITH(format, "shift_rm"));
|
|
PrintShiftRm(instr);
|
|
return 8;
|
|
}
|
|
} else if (format[1] == 'w') { // 'swi
|
|
ASSERT(STRING_STARTS_WITH(format, "swi"));
|
|
PrintSoftwareInterrupt(instr->SwiField());
|
|
return 3;
|
|
} else if (format[1] == 'i') { // 'sign: signed extra loads and stores
|
|
ASSERT(STRING_STARTS_WITH(format, "sign"));
|
|
if (instr->HasSign()) {
|
|
Print("s");
|
|
}
|
|
return 4;
|
|
}
|
|
// 's: S field of data processing instructions
|
|
if (instr->HasS()) {
|
|
Print("s");
|
|
}
|
|
return 1;
|
|
}
|
|
case 't': { // 'target: target of branch instructions
|
|
ASSERT(STRING_STARTS_WITH(format, "target"));
|
|
int off = (instr->SImmed24Field() << 2) + 8;
|
|
out_buffer_pos_ += v8i::OS::SNPrintF(
|
|
out_buffer_ + out_buffer_pos_,
|
|
"%+d -> %s",
|
|
off,
|
|
converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + off));
|
|
return 6;
|
|
}
|
|
case 'u': { // 'u: signed or unsigned multiplies
|
|
// The manual gets the meaning of bit 22 backwards in the multiply
|
|
// instruction overview on page A3.16.2. The instructions that
|
|
// exist in u and s variants are the following:
|
|
// smull A4.1.87
|
|
// umull A4.1.129
|
|
// umlal A4.1.128
|
|
// smlal A4.1.76
|
|
// For these 0 means u and 1 means s. As can be seen on their individual
|
|
// pages. The other 18 mul instructions have the bit set or unset in
|
|
// arbitrary ways that are unrelated to the signedness of the instruction.
|
|
// None of these 18 instructions exist in both a 'u' and an 's' variant.
|
|
|
|
if (instr->Bit(22) == 0) {
|
|
Print("u");
|
|
} else {
|
|
Print("s");
|
|
}
|
|
return 1;
|
|
}
|
|
case 'v': {
|
|
return FormatVFPinstruction(instr, format);
|
|
}
|
|
case 'S':
|
|
case 'D': {
|
|
return FormatVFPRegister(instr, format);
|
|
}
|
|
case 'w': { // 'w: W field of load and store instructions
|
|
if (instr->HasW()) {
|
|
Print("!");
|
|
}
|
|
return 1;
|
|
}
|
|
default: {
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
UNREACHABLE();
|
|
return -1;
|
|
}
|
|
|
|
|
|
// Format takes a formatting string for a whole instruction and prints it into
|
|
// the output buffer. All escaped options are handed to FormatOption to be
|
|
// parsed further.
|
|
void Decoder::Format(Instr* instr, const char* format) {
|
|
char cur = *format++;
|
|
while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
|
|
if (cur == '\'') { // Single quote is used as the formatting escape.
|
|
format += FormatOption(instr, format);
|
|
} else {
|
|
out_buffer_[out_buffer_pos_++] = cur;
|
|
}
|
|
cur = *format++;
|
|
}
|
|
out_buffer_[out_buffer_pos_] = '\0';
|
|
}
|
|
|
|
|
|
// For currently unimplemented decodings the disassembler calls Unknown(instr)
|
|
// which will just print "unknown" of the instruction bits.
|
|
void Decoder::Unknown(Instr* instr) {
|
|
Format(instr, "unknown");
|
|
}
|
|
|
|
|
|
void Decoder::DecodeType01(Instr* instr) {
|
|
int type = instr->TypeField();
|
|
if ((type == 0) && instr->IsSpecialType0()) {
|
|
// multiply instruction or extra loads and stores
|
|
if (instr->Bits(7, 4) == 9) {
|
|
if (instr->Bit(24) == 0) {
|
|
// multiply instructions
|
|
if (instr->Bit(23) == 0) {
|
|
if (instr->Bit(21) == 0) {
|
|
// The MUL instruction description (A 4.1.33) refers to Rd as being
|
|
// the destination for the operation, but it confusingly uses the
|
|
// Rn field to encode it.
|
|
Format(instr, "mul'cond's 'rn, 'rm, 'rs");
|
|
} else {
|
|
// The MLA instruction description (A 4.1.28) refers to the order
|
|
// of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
|
|
// Rn field to encode the Rd register and the Rd field to encode
|
|
// the Rn register.
|
|
Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
|
|
}
|
|
} else {
|
|
// The signed/long multiply instructions use the terms RdHi and RdLo
|
|
// when referring to the target registers. They are mapped to the Rn
|
|
// and Rd fields as follows:
|
|
// RdLo == Rd field
|
|
// RdHi == Rn field
|
|
// The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs>
|
|
Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs");
|
|
}
|
|
} else {
|
|
Unknown(instr); // not used by V8
|
|
}
|
|
} else if ((instr->Bit(20) == 0) && ((instr->Bits(7, 4) & 0xd) == 0xd)) {
|
|
// ldrd, strd
|
|
switch (instr->PUField()) {
|
|
case 0: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond's 'rd, ['rn], -'rm");
|
|
} else {
|
|
Format(instr, "'memop'cond's 'rd, ['rn], #-'off8");
|
|
}
|
|
break;
|
|
}
|
|
case 1: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond's 'rd, ['rn], +'rm");
|
|
} else {
|
|
Format(instr, "'memop'cond's 'rd, ['rn], #+'off8");
|
|
}
|
|
break;
|
|
}
|
|
case 2: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w");
|
|
} else {
|
|
Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w");
|
|
}
|
|
break;
|
|
}
|
|
case 3: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w");
|
|
} else {
|
|
Format(instr, "'memop'cond's 'rd, ['rn, #+'off8]'w");
|
|
}
|
|
break;
|
|
}
|
|
default: {
|
|
// The PU field is a 2-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
// extra load/store instructions
|
|
switch (instr->PUField()) {
|
|
case 0: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
|
|
} else {
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
|
|
}
|
|
break;
|
|
}
|
|
case 1: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
|
|
} else {
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
|
|
}
|
|
break;
|
|
}
|
|
case 2: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
|
|
} else {
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
|
|
}
|
|
break;
|
|
}
|
|
case 3: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
|
|
} else {
|
|
Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
|
|
}
|
|
break;
|
|
}
|
|
default: {
|
|
// The PU field is a 2-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
} else if ((type == 0) && instr->IsMiscType0()) {
|
|
if (instr->Bits(22, 21) == 1) {
|
|
switch (instr->Bits(7, 4)) {
|
|
case BX:
|
|
Format(instr, "bx'cond 'rm");
|
|
break;
|
|
case BLX:
|
|
Format(instr, "blx'cond 'rm");
|
|
break;
|
|
case BKPT:
|
|
Format(instr, "bkpt 'off0to3and8to19");
|
|
break;
|
|
default:
|
|
Unknown(instr); // not used by V8
|
|
break;
|
|
}
|
|
} else if (instr->Bits(22, 21) == 3) {
|
|
switch (instr->Bits(7, 4)) {
|
|
case CLZ:
|
|
Format(instr, "clz'cond 'rd, 'rm");
|
|
break;
|
|
default:
|
|
Unknown(instr); // not used by V8
|
|
break;
|
|
}
|
|
} else {
|
|
Unknown(instr); // not used by V8
|
|
}
|
|
} else {
|
|
switch (instr->OpcodeField()) {
|
|
case AND: {
|
|
Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case EOR: {
|
|
Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case SUB: {
|
|
Format(instr, "sub'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case RSB: {
|
|
Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case ADD: {
|
|
Format(instr, "add'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case ADC: {
|
|
Format(instr, "adc'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case SBC: {
|
|
Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case RSC: {
|
|
Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case TST: {
|
|
if (instr->HasS()) {
|
|
Format(instr, "tst'cond 'rn, 'shift_op");
|
|
} else {
|
|
Format(instr, "movw'cond 'mw");
|
|
}
|
|
break;
|
|
}
|
|
case TEQ: {
|
|
if (instr->HasS()) {
|
|
Format(instr, "teq'cond 'rn, 'shift_op");
|
|
} else {
|
|
// Other instructions matching this pattern are handled in the
|
|
// miscellaneous instructions part above.
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
}
|
|
case CMP: {
|
|
if (instr->HasS()) {
|
|
Format(instr, "cmp'cond 'rn, 'shift_op");
|
|
} else {
|
|
Format(instr, "movt'cond 'mw");
|
|
}
|
|
break;
|
|
}
|
|
case CMN: {
|
|
if (instr->HasS()) {
|
|
Format(instr, "cmn'cond 'rn, 'shift_op");
|
|
} else {
|
|
// Other instructions matching this pattern are handled in the
|
|
// miscellaneous instructions part above.
|
|
UNREACHABLE();
|
|
}
|
|
break;
|
|
}
|
|
case ORR: {
|
|
Format(instr, "orr'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case MOV: {
|
|
Format(instr, "mov'cond's 'rd, 'shift_op");
|
|
break;
|
|
}
|
|
case BIC: {
|
|
Format(instr, "bic'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case MVN: {
|
|
Format(instr, "mvn'cond's 'rd, 'shift_op");
|
|
break;
|
|
}
|
|
default: {
|
|
// The Opcode field is a 4-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeType2(Instr* instr) {
|
|
switch (instr->PUField()) {
|
|
case 0: {
|
|
if (instr->HasW()) {
|
|
Unknown(instr); // not used in V8
|
|
}
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
|
|
break;
|
|
}
|
|
case 1: {
|
|
if (instr->HasW()) {
|
|
Unknown(instr); // not used in V8
|
|
}
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
|
|
break;
|
|
}
|
|
case 2: {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
|
|
break;
|
|
}
|
|
case 3: {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
|
|
break;
|
|
}
|
|
default: {
|
|
// The PU field is a 2-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeType3(Instr* instr) {
|
|
switch (instr->PUField()) {
|
|
case 0: {
|
|
ASSERT(!instr->HasW());
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
|
|
break;
|
|
}
|
|
case 1: {
|
|
if (instr->HasW()) {
|
|
ASSERT(instr->Bits(5, 4) == 0x1);
|
|
if (instr->Bit(22) == 0x1) {
|
|
Format(instr, "usat 'rd, 'imm05@16, 'rm'shift_sat");
|
|
} else {
|
|
UNREACHABLE(); // SSAT.
|
|
}
|
|
} else {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
|
|
}
|
|
break;
|
|
}
|
|
case 2: {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
|
|
break;
|
|
}
|
|
case 3: {
|
|
if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
|
|
uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
|
|
uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
|
|
uint32_t msbit = widthminus1 + lsbit;
|
|
if (msbit <= 31) {
|
|
if (instr->Bit(22)) {
|
|
Format(instr, "ubfx'cond 'rd, 'rm, 'f");
|
|
} else {
|
|
Format(instr, "sbfx'cond 'rd, 'rm, 'f");
|
|
}
|
|
} else {
|
|
UNREACHABLE();
|
|
}
|
|
} else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) {
|
|
uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
|
|
uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16));
|
|
if (msbit >= lsbit) {
|
|
if (instr->RmField() == 15) {
|
|
Format(instr, "bfc'cond 'rd, 'f");
|
|
} else {
|
|
Format(instr, "bfi'cond 'rd, 'rm, 'f");
|
|
}
|
|
} else {
|
|
UNREACHABLE();
|
|
}
|
|
} else {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
|
|
}
|
|
break;
|
|
}
|
|
default: {
|
|
// The PU field is a 2-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeType4(Instr* instr) {
|
|
ASSERT(instr->Bit(22) == 0); // Privileged mode currently not supported.
|
|
if (instr->HasL()) {
|
|
Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
|
|
} else {
|
|
Format(instr, "stm'cond'pu 'rn'w, 'rlist");
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeType5(Instr* instr) {
|
|
Format(instr, "b'l'cond 'target");
|
|
}
|
|
|
|
|
|
void Decoder::DecodeType6(Instr* instr) {
|
|
DecodeType6CoprocessorIns(instr);
|
|
}
|
|
|
|
|
|
void Decoder::DecodeType7(Instr* instr) {
|
|
if (instr->Bit(24) == 1) {
|
|
Format(instr, "swi'cond 'swi");
|
|
} else {
|
|
DecodeTypeVFP(instr);
|
|
}
|
|
}
|
|
|
|
void Decoder::DecodeUnconditional(Instr* instr) {
|
|
if (instr->Bits(7, 4) == 0xB && instr->Bits(27, 25) == 0 && instr->HasL()) {
|
|
Format(instr, "'memop'h'pu 'rd, ");
|
|
bool immediate = instr->HasB();
|
|
switch (instr->PUField()) {
|
|
case 0: {
|
|
// Post index, negative.
|
|
if (instr->HasW()) {
|
|
Unknown(instr);
|
|
break;
|
|
}
|
|
if (immediate) {
|
|
Format(instr, "['rn], #-'imm12");
|
|
} else {
|
|
Format(instr, "['rn], -'rm");
|
|
}
|
|
break;
|
|
}
|
|
case 1: {
|
|
// Post index, positive.
|
|
if (instr->HasW()) {
|
|
Unknown(instr);
|
|
break;
|
|
}
|
|
if (immediate) {
|
|
Format(instr, "['rn], #+'imm12");
|
|
} else {
|
|
Format(instr, "['rn], +'rm");
|
|
}
|
|
break;
|
|
}
|
|
case 2: {
|
|
// Pre index or offset, negative.
|
|
if (immediate) {
|
|
Format(instr, "['rn, #-'imm12]'w");
|
|
} else {
|
|
Format(instr, "['rn, -'rm]'w");
|
|
}
|
|
break;
|
|
}
|
|
case 3: {
|
|
// Pre index or offset, positive.
|
|
if (immediate) {
|
|
Format(instr, "['rn, #+'imm12]'w");
|
|
} else {
|
|
Format(instr, "['rn, +'rm]'w");
|
|
}
|
|
break;
|
|
}
|
|
default: {
|
|
// The PU field is a 2-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
Format(instr, "break 'msg");
|
|
}
|
|
|
|
|
|
// void Decoder::DecodeTypeVFP(Instr* instr)
|
|
// vmov: Sn = Rt
|
|
// vmov: Rt = Sn
|
|
// vcvt: Dd = Sm
|
|
// vcvt: Sd = Dm
|
|
// Dd = vadd(Dn, Dm)
|
|
// Dd = vsub(Dn, Dm)
|
|
// Dd = vmul(Dn, Dm)
|
|
// Dd = vdiv(Dn, Dm)
|
|
// vcmp(Dd, Dm)
|
|
// vmrs
|
|
// Dd = vsqrt(Dm)
|
|
void Decoder::DecodeTypeVFP(Instr* instr) {
|
|
ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) );
|
|
ASSERT(instr->Bits(11, 9) == 0x5);
|
|
|
|
if (instr->Bit(4) == 0) {
|
|
if (instr->Opc1Field() == 0x7) {
|
|
// Other data processing instructions
|
|
if ((instr->Opc2Field() == 0x0) && (instr->Opc3Field() == 0x1)) {
|
|
// vmov register to register.
|
|
if (instr->SzField() == 0x1) {
|
|
Format(instr, "vmov.f64'cond 'Dd, 'Dm");
|
|
} else {
|
|
Format(instr, "vmov.f32'cond 'Sd, 'Sm");
|
|
}
|
|
} else if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) {
|
|
DecodeVCVTBetweenDoubleAndSingle(instr);
|
|
} else if ((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) {
|
|
DecodeVCVTBetweenFloatingPointAndInteger(instr);
|
|
} else if (((instr->Opc2Field() >> 1) == 0x6) &&
|
|
(instr->Opc3Field() & 0x1)) {
|
|
DecodeVCVTBetweenFloatingPointAndInteger(instr);
|
|
} else if (((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) &&
|
|
(instr->Opc3Field() & 0x1)) {
|
|
DecodeVCMP(instr);
|
|
} else if (((instr->Opc2Field() == 0x1)) && (instr->Opc3Field() == 0x3)) {
|
|
Format(instr, "vsqrt.f64'cond 'Dd, 'Dm");
|
|
} else if (instr->Opc3Field() == 0x0) {
|
|
if (instr->SzField() == 0x1) {
|
|
Format(instr, "vmov.f64'cond 'Dd, 'd");
|
|
} else {
|
|
Unknown(instr); // Not used by V8.
|
|
}
|
|
} else {
|
|
Unknown(instr); // Not used by V8.
|
|
}
|
|
} else if (instr->Opc1Field() == 0x3) {
|
|
if (instr->SzField() == 0x1) {
|
|
if (instr->Opc3Field() & 0x1) {
|
|
Format(instr, "vsub.f64'cond 'Dd, 'Dn, 'Dm");
|
|
} else {
|
|
Format(instr, "vadd.f64'cond 'Dd, 'Dn, 'Dm");
|
|
}
|
|
} else {
|
|
Unknown(instr); // Not used by V8.
|
|
}
|
|
} else if ((instr->Opc1Field() == 0x2) && !(instr->Opc3Field() & 0x1)) {
|
|
if (instr->SzField() == 0x1) {
|
|
Format(instr, "vmul.f64'cond 'Dd, 'Dn, 'Dm");
|
|
} else {
|
|
Unknown(instr); // Not used by V8.
|
|
}
|
|
} else if ((instr->Opc1Field() == 0x4) && !(instr->Opc3Field() & 0x1)) {
|
|
if (instr->SzField() == 0x1) {
|
|
Format(instr, "vdiv.f64'cond 'Dd, 'Dn, 'Dm");
|
|
} else {
|
|
Unknown(instr); // Not used by V8.
|
|
}
|
|
} else {
|
|
Unknown(instr); // Not used by V8.
|
|
}
|
|
} else {
|
|
if ((instr->VCField() == 0x0) &&
|
|
(instr->VAField() == 0x0)) {
|
|
DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
|
|
} else if ((instr->VLField() == 0x1) &&
|
|
(instr->VCField() == 0x0) &&
|
|
(instr->VAField() == 0x7) &&
|
|
(instr->Bits(19, 16) == 0x1)) {
|
|
if (instr->Bits(15, 12) == 0xF)
|
|
Format(instr, "vmrs'cond APSR, FPSCR");
|
|
else
|
|
Unknown(instr); // Not used by V8.
|
|
} else {
|
|
Unknown(instr); // Not used by V8.
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr) {
|
|
ASSERT((instr->Bit(4) == 1) && (instr->VCField() == 0x0) &&
|
|
(instr->VAField() == 0x0));
|
|
|
|
bool to_arm_register = (instr->VLField() == 0x1);
|
|
|
|
if (to_arm_register) {
|
|
Format(instr, "vmov'cond 'rt, 'Sn");
|
|
} else {
|
|
Format(instr, "vmov'cond 'Sn, 'rt");
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeVCMP(Instr* instr) {
|
|
ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
|
|
ASSERT(((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) &&
|
|
(instr->Opc3Field() & 0x1));
|
|
|
|
// Comparison.
|
|
bool dp_operation = (instr->SzField() == 1);
|
|
bool raise_exception_for_qnan = (instr->Bit(7) == 0x1);
|
|
|
|
if (dp_operation && !raise_exception_for_qnan) {
|
|
if (instr->Opc2Field() == 0x4) {
|
|
Format(instr, "vcmp.f64'cond 'Dd, 'Dm");
|
|
} else if (instr->Opc2Field() == 0x5) {
|
|
Format(instr, "vcmp.f64'cond 'Dd, #0.0");
|
|
} else {
|
|
Unknown(instr); // invalid
|
|
}
|
|
} else {
|
|
Unknown(instr); // Not used by V8.
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instr* instr) {
|
|
ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
|
|
ASSERT((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3));
|
|
|
|
bool double_to_single = (instr->SzField() == 1);
|
|
|
|
if (double_to_single) {
|
|
Format(instr, "vcvt.f32.f64'cond 'Sd, 'Dm");
|
|
} else {
|
|
Format(instr, "vcvt.f64.f32'cond 'Dd, 'Sm");
|
|
}
|
|
}
|
|
|
|
|
|
void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instr* instr) {
|
|
ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
|
|
ASSERT(((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) ||
|
|
(((instr->Opc2Field() >> 1) == 0x6) && (instr->Opc3Field() & 0x1)));
|
|
|
|
bool to_integer = (instr->Bit(18) == 1);
|
|
bool dp_operation = (instr->SzField() == 1);
|
|
if (to_integer) {
|
|
bool unsigned_integer = (instr->Bit(16) == 0);
|
|
|
|
if (dp_operation) {
|
|
if (unsigned_integer) {
|
|
Format(instr, "vcvt.u32.f64'cond 'Sd, 'Dm");
|
|
} else {
|
|
Format(instr, "vcvt.s32.f64'cond 'Sd, 'Dm");
|
|
}
|
|
} else {
|
|
if (unsigned_integer) {
|
|
Format(instr, "vcvt.u32.f32'cond 'Sd, 'Sm");
|
|
} else {
|
|
Format(instr, "vcvt.s32.f32'cond 'Sd, 'Sm");
|
|
}
|
|
}
|
|
} else {
|
|
bool unsigned_integer = (instr->Bit(7) == 0);
|
|
|
|
if (dp_operation) {
|
|
if (unsigned_integer) {
|
|
Format(instr, "vcvt.f64.u32'cond 'Dd, 'Sm");
|
|
} else {
|
|
Format(instr, "vcvt.f64.s32'cond 'Dd, 'Sm");
|
|
}
|
|
} else {
|
|
if (unsigned_integer) {
|
|
Format(instr, "vcvt.f32.u32'cond 'Sd, 'Sm");
|
|
} else {
|
|
Format(instr, "vcvt.f32.s32'cond 'Sd, 'Sm");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
// Decode Type 6 coprocessor instructions.
|
|
// Dm = vmov(Rt, Rt2)
|
|
// <Rt, Rt2> = vmov(Dm)
|
|
// Ddst = MEM(Rbase + 4*offset).
|
|
// MEM(Rbase + 4*offset) = Dsrc.
|
|
void Decoder::DecodeType6CoprocessorIns(Instr* instr) {
|
|
ASSERT((instr->TypeField() == 6));
|
|
|
|
if (instr->CoprocessorField() == 0xA) {
|
|
switch (instr->OpcodeField()) {
|
|
case 0x8:
|
|
if (instr->HasL()) {
|
|
Format(instr, "vldr'cond 'Sd, ['rn - 4*'off8]");
|
|
} else {
|
|
Format(instr, "vstr'cond 'Sd, ['rn - 4*'off8]");
|
|
}
|
|
break;
|
|
case 0xC:
|
|
if (instr->HasL()) {
|
|
Format(instr, "vldr'cond 'Sd, ['rn + 4*'off8]");
|
|
} else {
|
|
Format(instr, "vstr'cond 'Sd, ['rn + 4*'off8]");
|
|
}
|
|
break;
|
|
default:
|
|
Unknown(instr); // Not used by V8.
|
|
break;
|
|
}
|
|
} else if (instr->CoprocessorField() == 0xB) {
|
|
switch (instr->OpcodeField()) {
|
|
case 0x2:
|
|
// Load and store double to two GP registers
|
|
if (instr->Bits(7, 4) != 0x1) {
|
|
Unknown(instr); // Not used by V8.
|
|
} else if (instr->HasL()) {
|
|
Format(instr, "vmov'cond 'rt, 'rn, 'Dm");
|
|
} else {
|
|
Format(instr, "vmov'cond 'Dm, 'rt, 'rn");
|
|
}
|
|
break;
|
|
case 0x8:
|
|
if (instr->HasL()) {
|
|
Format(instr, "vldr'cond 'Dd, ['rn - 4*'off8]");
|
|
} else {
|
|
Format(instr, "vstr'cond 'Dd, ['rn - 4*'off8]");
|
|
}
|
|
break;
|
|
case 0xC:
|
|
if (instr->HasL()) {
|
|
Format(instr, "vldr'cond 'Dd, ['rn + 4*'off8]");
|
|
} else {
|
|
Format(instr, "vstr'cond 'Dd, ['rn + 4*'off8]");
|
|
}
|
|
break;
|
|
default:
|
|
Unknown(instr); // Not used by V8.
|
|
break;
|
|
}
|
|
} else {
|
|
UNIMPLEMENTED(); // Not used by V8.
|
|
}
|
|
}
|
|
|
|
|
|
// Disassemble the instruction at *instr_ptr into the output buffer.
|
|
int Decoder::InstructionDecode(byte* instr_ptr) {
|
|
Instr* instr = Instr::At(instr_ptr);
|
|
// Print raw instruction bytes.
|
|
out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
|
|
"%08x ",
|
|
instr->InstructionBits());
|
|
if (instr->ConditionField() == special_condition) {
|
|
DecodeUnconditional(instr);
|
|
return Instr::kInstrSize;
|
|
}
|
|
switch (instr->TypeField()) {
|
|
case 0:
|
|
case 1: {
|
|
DecodeType01(instr);
|
|
break;
|
|
}
|
|
case 2: {
|
|
DecodeType2(instr);
|
|
break;
|
|
}
|
|
case 3: {
|
|
DecodeType3(instr);
|
|
break;
|
|
}
|
|
case 4: {
|
|
DecodeType4(instr);
|
|
break;
|
|
}
|
|
case 5: {
|
|
DecodeType5(instr);
|
|
break;
|
|
}
|
|
case 6: {
|
|
DecodeType6(instr);
|
|
break;
|
|
}
|
|
case 7: {
|
|
DecodeType7(instr);
|
|
break;
|
|
}
|
|
default: {
|
|
// The type field is 3-bits in the ARM encoding.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
return Instr::kInstrSize;
|
|
}
|
|
|
|
|
|
} } // namespace assembler::arm
|
|
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
namespace disasm {
|
|
|
|
namespace v8i = v8::internal;
|
|
|
|
|
|
const char* NameConverter::NameOfAddress(byte* addr) const {
|
|
static v8::internal::EmbeddedVector<char, 32> tmp_buffer;
|
|
v8::internal::OS::SNPrintF(tmp_buffer, "%p", addr);
|
|
return tmp_buffer.start();
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameOfConstant(byte* addr) const {
|
|
return NameOfAddress(addr);
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameOfCPURegister(int reg) const {
|
|
return assembler::arm::Registers::Name(reg);
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameOfByteCPURegister(int reg) const {
|
|
UNREACHABLE(); // ARM does not have the concept of a byte register
|
|
return "nobytereg";
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameOfXMMRegister(int reg) const {
|
|
UNREACHABLE(); // ARM does not have any XMM registers
|
|
return "noxmmreg";
|
|
}
|
|
|
|
|
|
const char* NameConverter::NameInCode(byte* addr) const {
|
|
// The default name converter is called for unknown code. So we will not try
|
|
// to access any memory.
|
|
return "";
|
|
}
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
|
|
Disassembler::Disassembler(const NameConverter& converter)
|
|
: converter_(converter) {}
|
|
|
|
|
|
Disassembler::~Disassembler() {}
|
|
|
|
|
|
int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
|
|
byte* instruction) {
|
|
assembler::arm::Decoder d(converter_, buffer);
|
|
return d.InstructionDecode(instruction);
|
|
}
|
|
|
|
|
|
int Disassembler::ConstantPoolSizeAt(byte* instruction) {
|
|
int instruction_bits = *(reinterpret_cast<int*>(instruction));
|
|
if ((instruction_bits & 0xfff00000) == 0x03000000) {
|
|
return instruction_bits & 0x0000ffff;
|
|
} else {
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
|
|
void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
|
|
NameConverter converter;
|
|
Disassembler d(converter);
|
|
for (byte* pc = begin; pc < end;) {
|
|
v8::internal::EmbeddedVector<char, 128> buffer;
|
|
buffer[0] = '\0';
|
|
byte* prev_pc = pc;
|
|
pc += d.InstructionDecode(buffer, pc);
|
|
fprintf(f, "%p %08x %s\n",
|
|
prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
|
|
}
|
|
}
|
|
|
|
|
|
} // namespace disasm
|
|
|
|
#endif // V8_TARGET_ARCH_ARM
|