e66f276e46
dependent, so we push it down to the architecture dependent files. Currently all architectures visit in almost the same way, but this is about to change on ARM with movw/movt. Review URL: http://codereview.chromium.org/2218002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4721 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
395 lines
11 KiB
C++
395 lines
11 KiB
C++
// Copyright 2009 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef V8_X64_ASSEMBLER_X64_INL_H_
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#define V8_X64_ASSEMBLER_X64_INL_H_
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#include "cpu.h"
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#include "debug.h"
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#include "memory.h"
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namespace v8 {
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namespace internal {
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inline Condition NegateCondition(Condition cc) {
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return static_cast<Condition>(cc ^ 1);
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}
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// -----------------------------------------------------------------------------
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// Implementation of Assembler
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void Assembler::emitl(uint32_t x) {
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Memory::uint32_at(pc_) = x;
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pc_ += sizeof(uint32_t);
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}
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void Assembler::emitq(uint64_t x, RelocInfo::Mode rmode) {
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Memory::uint64_at(pc_) = x;
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if (rmode != RelocInfo::NONE) {
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RecordRelocInfo(rmode, x);
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}
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pc_ += sizeof(uint64_t);
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}
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void Assembler::emitw(uint16_t x) {
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Memory::uint16_at(pc_) = x;
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pc_ += sizeof(uint16_t);
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}
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void Assembler::emit_code_target(Handle<Code> target, RelocInfo::Mode rmode) {
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ASSERT(RelocInfo::IsCodeTarget(rmode));
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RecordRelocInfo(rmode);
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int current = code_targets_.length();
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if (current > 0 && code_targets_.last().is_identical_to(target)) {
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// Optimization if we keep jumping to the same code target.
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emitl(current - 1);
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} else {
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code_targets_.Add(target);
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emitl(current);
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}
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}
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void Assembler::emit_rex_64(Register reg, Register rm_reg) {
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emit(0x48 | reg.high_bit() << 2 | rm_reg.high_bit());
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}
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void Assembler::emit_rex_64(XMMRegister reg, Register rm_reg) {
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emit(0x48 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3);
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}
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void Assembler::emit_rex_64(Register reg, XMMRegister rm_reg) {
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emit(0x48 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3);
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}
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void Assembler::emit_rex_64(Register reg, const Operand& op) {
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emit(0x48 | reg.high_bit() << 2 | op.rex_);
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}
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void Assembler::emit_rex_64(XMMRegister reg, const Operand& op) {
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emit(0x48 | (reg.code() & 0x8) >> 1 | op.rex_);
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}
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void Assembler::emit_rex_64(Register rm_reg) {
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ASSERT_EQ(rm_reg.code() & 0xf, rm_reg.code());
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emit(0x48 | rm_reg.high_bit());
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}
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void Assembler::emit_rex_64(const Operand& op) {
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emit(0x48 | op.rex_);
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}
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void Assembler::emit_rex_32(Register reg, Register rm_reg) {
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emit(0x40 | reg.high_bit() << 2 | rm_reg.high_bit());
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}
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void Assembler::emit_rex_32(Register reg, const Operand& op) {
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emit(0x40 | reg.high_bit() << 2 | op.rex_);
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}
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void Assembler::emit_rex_32(Register rm_reg) {
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emit(0x40 | rm_reg.high_bit());
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}
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void Assembler::emit_rex_32(const Operand& op) {
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emit(0x40 | op.rex_);
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}
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void Assembler::emit_optional_rex_32(Register reg, Register rm_reg) {
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byte rex_bits = reg.high_bit() << 2 | rm_reg.high_bit();
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if (rex_bits != 0) emit(0x40 | rex_bits);
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}
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void Assembler::emit_optional_rex_32(Register reg, const Operand& op) {
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byte rex_bits = reg.high_bit() << 2 | op.rex_;
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if (rex_bits != 0) emit(0x40 | rex_bits);
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}
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void Assembler::emit_optional_rex_32(XMMRegister reg, const Operand& op) {
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byte rex_bits = (reg.code() & 0x8) >> 1 | op.rex_;
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if (rex_bits != 0) emit(0x40 | rex_bits);
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}
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void Assembler::emit_optional_rex_32(XMMRegister reg, XMMRegister base) {
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byte rex_bits = (reg.code() & 0x8) >> 1 | (base.code() & 0x8) >> 3;
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if (rex_bits != 0) emit(0x40 | rex_bits);
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}
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void Assembler::emit_optional_rex_32(XMMRegister reg, Register base) {
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byte rex_bits = (reg.code() & 0x8) >> 1 | (base.code() & 0x8) >> 3;
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if (rex_bits != 0) emit(0x40 | rex_bits);
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}
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void Assembler::emit_optional_rex_32(Register reg, XMMRegister base) {
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byte rex_bits = (reg.code() & 0x8) >> 1 | (base.code() & 0x8) >> 3;
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if (rex_bits != 0) emit(0x40 | rex_bits);
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}
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void Assembler::emit_optional_rex_32(Register rm_reg) {
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if (rm_reg.high_bit()) emit(0x41);
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}
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void Assembler::emit_optional_rex_32(const Operand& op) {
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if (op.rex_ != 0) emit(0x40 | op.rex_);
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}
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Address Assembler::target_address_at(Address pc) {
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return Memory::int32_at(pc) + pc + 4;
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}
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void Assembler::set_target_address_at(Address pc, Address target) {
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Memory::int32_at(pc) = static_cast<int32_t>(target - pc - 4);
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CPU::FlushICache(pc, sizeof(int32_t));
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}
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Handle<Object> Assembler::code_target_object_handle_at(Address pc) {
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return code_targets_[Memory::int32_at(pc)];
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}
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// -----------------------------------------------------------------------------
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// Implementation of RelocInfo
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// The modes possibly affected by apply must be in kApplyMask.
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void RelocInfo::apply(intptr_t delta) {
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if (IsInternalReference(rmode_)) {
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// absolute code pointer inside code object moves with the code object.
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Memory::Address_at(pc_) += static_cast<int32_t>(delta);
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} else if (IsCodeTarget(rmode_)) {
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Memory::int32_at(pc_) -= static_cast<int32_t>(delta);
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} else if (rmode_ == JS_RETURN && IsPatchedReturnSequence()) {
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// Special handling of js_return when a break point is set (call
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// instruction has been inserted).
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Memory::int32_at(pc_ + 1) -= static_cast<int32_t>(delta); // relocate entry
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}
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}
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Address RelocInfo::target_address() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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if (IsCodeTarget(rmode_)) {
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return Assembler::target_address_at(pc_);
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} else {
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return Memory::Address_at(pc_);
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}
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}
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Address RelocInfo::target_address_address() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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return reinterpret_cast<Address>(pc_);
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}
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int RelocInfo::target_address_size() {
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if (IsCodedSpecially()) {
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return Assembler::kCallTargetSize;
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} else {
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return Assembler::kExternalTargetSize;
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}
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}
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void RelocInfo::set_target_address(Address target) {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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if (IsCodeTarget(rmode_)) {
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Assembler::set_target_address_at(pc_, target);
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} else {
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Memory::Address_at(pc_) = target;
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}
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}
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Object* RelocInfo::target_object() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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return Memory::Object_at(pc_);
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}
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Handle<Object> RelocInfo::target_object_handle(Assembler *origin) {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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if (rmode_ == EMBEDDED_OBJECT) {
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return Memory::Object_Handle_at(pc_);
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} else {
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return origin->code_target_object_handle_at(pc_);
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}
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}
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Object** RelocInfo::target_object_address() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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return reinterpret_cast<Object**>(pc_);
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}
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Address* RelocInfo::target_reference_address() {
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ASSERT(rmode_ == RelocInfo::EXTERNAL_REFERENCE);
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return reinterpret_cast<Address*>(pc_);
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}
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void RelocInfo::set_target_object(Object* target) {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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*reinterpret_cast<Object**>(pc_) = target;
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}
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bool RelocInfo::IsPatchedReturnSequence() {
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// The recognized call sequence is:
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// movq(kScratchRegister, immediate64); call(kScratchRegister);
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// It only needs to be distinguished from a return sequence
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// movq(rsp, rbp); pop(rbp); ret(n); int3 *6
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// The 11th byte is int3 (0xCC) in the return sequence and
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// REX.WB (0x48+register bit) for the call sequence.
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#ifdef ENABLE_DEBUGGER_SUPPORT
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return pc_[10] != 0xCC;
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#else
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return false;
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#endif
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}
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Address RelocInfo::call_address() {
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ASSERT(IsPatchedReturnSequence());
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return Memory::Address_at(
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pc_ + Assembler::kRealPatchReturnSequenceAddressOffset);
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}
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void RelocInfo::set_call_address(Address target) {
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ASSERT(IsPatchedReturnSequence());
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Memory::Address_at(pc_ + Assembler::kRealPatchReturnSequenceAddressOffset) =
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target;
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}
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Object* RelocInfo::call_object() {
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ASSERT(IsPatchedReturnSequence());
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return *call_object_address();
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}
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void RelocInfo::set_call_object(Object* target) {
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ASSERT(IsPatchedReturnSequence());
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*call_object_address() = target;
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}
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Object** RelocInfo::call_object_address() {
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ASSERT(IsPatchedReturnSequence());
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return reinterpret_cast<Object**>(
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pc_ + Assembler::kPatchReturnSequenceAddressOffset);
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}
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void RelocInfo::Visit(ObjectVisitor* visitor) {
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RelocInfo::Mode mode = rmode();
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if (mode == RelocInfo::EMBEDDED_OBJECT) {
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visitor->VisitPointer(target_object_address());
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} else if (RelocInfo::IsCodeTarget(mode)) {
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visitor->VisitCodeTarget(this);
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} else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
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visitor->VisitExternalReference(target_reference_address());
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#ifdef ENABLE_DEBUGGER_SUPPORT
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} else if (Debug::has_break_points() &&
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RelocInfo::IsJSReturn(mode) &&
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IsPatchedReturnSequence()) {
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visitor->VisitDebugTarget(this);
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#endif
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} else if (mode == RelocInfo::RUNTIME_ENTRY) {
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visitor->VisitRuntimeEntry(this);
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}
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}
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// -----------------------------------------------------------------------------
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// Implementation of Operand
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void Operand::set_modrm(int mod, Register rm_reg) {
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ASSERT(is_uint2(mod));
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buf_[0] = mod << 6 | rm_reg.low_bits();
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// Set REX.B to the high bit of rm.code().
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rex_ |= rm_reg.high_bit();
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}
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void Operand::set_sib(ScaleFactor scale, Register index, Register base) {
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ASSERT(len_ == 1);
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ASSERT(is_uint2(scale));
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// Use SIB with no index register only for base rsp or r12. Otherwise we
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// would skip the SIB byte entirely.
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ASSERT(!index.is(rsp) || base.is(rsp) || base.is(r12));
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buf_[1] = scale << 6 | index.low_bits() << 3 | base.low_bits();
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rex_ |= index.high_bit() << 1 | base.high_bit();
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len_ = 2;
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}
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void Operand::set_disp8(int disp) {
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ASSERT(is_int8(disp));
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ASSERT(len_ == 1 || len_ == 2);
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int8_t* p = reinterpret_cast<int8_t*>(&buf_[len_]);
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*p = disp;
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len_ += sizeof(int8_t);
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}
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void Operand::set_disp32(int disp) {
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ASSERT(len_ == 1 || len_ == 2);
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int32_t* p = reinterpret_cast<int32_t*>(&buf_[len_]);
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*p = disp;
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len_ += sizeof(int32_t);
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}
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} } // namespace v8::internal
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#endif // V8_X64_ASSEMBLER_X64_INL_H_
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