v8/test/unittests/compiler/arm64
Ambroise Vincent 20945ef75d [turbofan] Add SIMD multiply-add/sub on arm64
Fold distinct MUL and ADD (or SUB) instructions into a single MLA (or
MLS) instruction, mirroring what is being done for general purpose
registers.

SIMD wasm only uses the vectorized ADD and MUL instructions on quad
vectors (NEON Q), so only those cases are handled.

SIMD wasm only uses MUL by vectors, not by elements so there is no need
to check for an addition and shift reduction.

Change-Id: If07191dde9fb1dc37a5de27187800c15cc4325ea
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2184239
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Commit-Queue: Martyn Capewell <martyn.capewell@arm.com>
Cr-Commit-Position: refs/heads/master@{#67770}
2020-05-13 09:40:00 +00:00
..
instruction-selector-arm64-unittest.cc [turbofan] Add SIMD multiply-add/sub on arm64 2020-05-13 09:40:00 +00:00