Fixed bug: makefile link steps always runs (triggered by prebuild and prelink)
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3cdd0d2442
commit
78c4c02997
@ -88,14 +88,12 @@ endif
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.PHONY: clean prebuild prelink
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<% if os.is("MacOSX") and this.kind == "WindowedApp" then %>
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all: $(TARGET) $(dir $(TARGETDIR))PkgInfo $(dir $(TARGETDIR))Info.plist
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$(dir $(TARGETDIR))PkgInfo:
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$(dir $(TARGETDIR))Info.plist:
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all: $(TARGETDIR) $(OBJDIR) prebuild $(OBJECTS) $(RESOURCES) prelink $(TARGET) $(dir $(TARGETDIR))PkgInfo $(dir $(TARGETDIR))Info.plist
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<% else %>
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all: $(TARGETDIR) $(OBJDIR) prebuild $(OBJECTS) $(RESOURCES) prelink $(TARGET)
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<% end %>
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$(TARGET): $(TARGETDIR) $(OBJDIR) prebuild $(OBJECTS) $(LDDEPS) $(RESOURCES) prelink
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$(TARGET): $(OBJECTS) $(LDDEPS) $(RESOURCES)
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@echo Linking <%= this.name %>
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@$(LINKCMD)
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$(POSTBUILDCMDS)
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@ -106,6 +104,12 @@ $(TARGETDIR):
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$(OBJDIR):
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$(MKDIR_RULE)
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<% if os.is("MacOSX") and this.kind == "WindowedApp" then %>
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$(dir $(TARGETDIR))PkgInfo:
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$(dir $(TARGETDIR))Info.plist:
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<% end %>
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clean:
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@echo Cleaning <%= this.name %>
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ifeq (posix,$(SHELLTYPE))
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@ -174,9 +174,9 @@ endif
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.PHONY: clean prebuild prelink
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all: $(TARGET) $(COPYFILES)
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all: $(TARGETDIR) $(OBJDIR) prebuild $(EMBEDFILES) $(COPYFILES) prelink $(TARGET)
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$(TARGET): $(TARGETDIR) $(OBJDIR) prebuild $(SOURCES) $(EMBEDFILES) $(DEPENDS) prelink
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$(TARGET): $(SOURCES) $(EMBEDFILES) $(DEPENDS)
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$(SILENT) $(CSC) /nologo /out:$@ $(FLAGS) $(REFERENCES) $(SOURCES) $(patsubst %,/resource:%,$(EMBEDFILES))
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$(POSTBUILDCMDS)
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