[*] Handhold non-MSVC compilers
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@ -118,12 +118,16 @@ namespace Aurora::Threading::Primitives
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auto &uValueRef = this->lock_.uWaitCount;
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#if defined(AURORA_ARCH_X86) || defined(AURORA_ARCH_X64)
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*(AuUInt8 *)&uValueRef = 0;
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#if defined(AURORA_COMPILER_MSVC)
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#if defined(AURORA_ARCH_X86) || defined(AURORA_ARCH_X64)
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*(AuUInt8 *)&uValueRef = 0;
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#else
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InterlockedAndRelease((volatile LONG *)&uValueRef, ~0xFF);
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#endif
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#else
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InterlockedAndRelease((volatile LONG *)&uValueRef, ~0xFF);
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__sync_lock_release((AuUInt8 *)&uValueRef);
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#endif
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while (true)
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{
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auto uOld = uValueRef;
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@ -273,31 +273,35 @@ namespace Aurora::Threading::Primitives
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auto &uValueRef = this->state_;
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#if defined(AURORA_ARCH_X86) || defined(AURORA_ARCH_X64)
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// Intel 64 and IA - 32 Architectures Software Developer's Manual, Volume 3A: Section: 8.2.3.1
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*(AuUInt8 *)&uValueRef = 0;
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#if defined(AURORA_COMPILER_MSVC)
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#if defined(AURORA_ARCH_X86) || defined(AURORA_ARCH_X64)
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// Intel 64 and IA - 32 Architectures Software Developer's Manual, Volume 3A: Section: 8.2.3.1
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*(AuUInt8 *)&uValueRef = 0;
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// From this point onwards, our thread could be subject to StoreLoad re-ordering
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// ...but it should not matter.
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// Given the memory model of x86[64], we can only really expect to be out of order during an unfenced load operation, which in this class, can only be expected under this function before the CAS.
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// No other place reads.
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// From this point onwards, our thread could be subject to StoreLoad re-ordering
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// ...but it should not matter.
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// Given the memory model of x86[64], we can only really expect to be out of order during an unfenced load operation, which in this class, can only be expected under this function before the CAS.
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// No other place reads.
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// Re-ordering race condition 1: one thread wins an atomic bit set, that we dont catch until the CAS, resulting in: a slow implicit fence under the cas, a mm_pause stall, a compare, and a return
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// alt: uValueRef reads zero, resulting in a preemptive return while no threads need to be awoken
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// Re-ordering race condition 2: we unlock, multiple threads enter ::Lock(), we somehow read `uValue = uValueRef` as zero, and then the first atomic bitsetandtest winner thread signals the keyed mutex
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// I fail to see how:
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// *byte = 0; | |
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// | interlocked atomicbitset | interlocked atomicbitset fail
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// | [logic] | interlocked atomic set kFutexBitWait
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// | *byte = 0; | yield
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// | auto uValue =[acquire]= uValueRef
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// ...would result in the second thread missing the third threads atomic set kFutexBitWait (cst (?) on the account of 8.2.3.1, 8.2.3.8, etc)
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// Re-ordering race condition 1: one thread wins an atomic bit set, that we dont catch until the CAS, resulting in: a slow implicit fence under the cas, a mm_pause stall, a compare, and a return
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// alt: uValueRef reads zero, resulting in a preemptive return while no threads need to be awoken
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// Re-ordering race condition 2: we unlock, multiple threads enter ::Lock(), we somehow read `uValue = uValueRef` as zero, and then the first atomic bitsetandtest winner thread signals the keyed mutex
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// I fail to see how:
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// *byte = 0; | |
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// | interlocked atomicbitset | interlocked atomicbitset fail
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// | [logic] | interlocked atomic set kFutexBitWait
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// | *byte = 0; | yield
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// | auto uValue =[acquire]= uValueRef
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// ...would result in the second thread missing the third threads atomic set kFutexBitWait (cst (?) on the account of 8.2.3.1, 8.2.3.8, etc)
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// Also note: mfence is far too expensive and the _ReadWriteBarrier() intrinsics do absolutely nothing
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_ReadWriteBarrier();
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// Also note: mfence is far too expensive and the _ReadWriteBarrier() intrinsics do absolutely nothing
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_ReadWriteBarrier();
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#else
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InterlockedAndRelease((volatile LONG *)&uValueRef, ~0xFF);
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#endif
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#else
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InterlockedAndRelease((volatile LONG *)&uValueRef, ~0xFF);
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__sync_lock_release((AuUInt8 *)&uValueRef); // __atomic_store_explicit((AuUInt8 *)&uValueRef, 0, __ATOMIC_RELEASE)
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#endif
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while (true)
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