/***
    Copyright (C) 2021 J Reece Wilson (a/k/a "Reece"). All rights reserved.

    File: CpuInfo.hpp
    Date: 2021-6-10
    Author: Reece
***/
#pragma once

namespace Aurora::HWInfo
{
    struct AUKN_SYM CpuId
    {
        bool SSE3();
        bool PCLMULQDQ();
        bool MONITOR();
        bool SSSE3();
        bool FMA();
        bool CMPXCHG16B();
        bool SSE41();
        bool SSE42();
        bool MOVBE();
        bool POPCNT();
        bool AES();
        bool XSAVE();
        bool OSXSAVE();
        bool AVX();
        bool F16C();
        bool RDRAND();
    
        bool MSR();
        bool CX8();
        bool SEP();
        bool CMOV();
        bool CLFSH();
        bool MMX();
        bool FXSR();
        bool SSE();
        bool SSE2();
    
        bool FSGSBASE();
        bool BMI1();
        bool HLE();
        bool AVX2();
        bool BMI2();
        bool ERMS();
        bool INVPCID();
        bool RTM();
        bool AVX512F();
        bool RDSEED();
        bool ADX();
        bool AVX512PF();
        bool AVX512ER();
        bool AVX512CD();
        bool SHA();
    
        bool PREFETCHWT1();
    
        bool LAHF();
        bool LZCNT();
        bool ABM();
        bool SSE4a();
        bool XOP();
        bool TBM();
    
        bool SYSCALL();
        bool MMXEXT();
        bool RDTSCP();
        bool _3DNOWEXT();
        bool _3DNOW();

        AuString vendor;
        AuString brand;
        bool isIntel;
        bool isAMD;
        AuUInt32 f_1_ECX;
        AuUInt32 f_1_EDX;
        AuUInt32 f_7_EBX;
        AuUInt32 f_7_ECX;
        AuUInt32 f_81_ECX;
        AuUInt32 f_81_EDX;
    };

    struct CpuInfo
    {
        Aurora::Build::EArchitecture cpuArch;

        AuUInt8 socket;
        AuUInt8 cores;
        AuUInt8 threads;
        
        CpuId cpuId;
    };

    AUKN_SYM const CpuInfo &GetCPUInfo();   
}