AuroraRuntime/Source/Threading
Jamie Reece Wilson 035d822ec1 [*] Explicit memory order access barrier when reading WOA_SEMAPHORE_MODE-less bAlive under weakly ordered systems. (5b193411 cont: "[*] Improve regressed AuWoA time to wake"
In all other cases, the memory is either thread-local write-local or followed up by an indirect aquire/release of the processors pipeline and L1 cache by virtue of the containers dumb spinlock ::Lock, ::Unlock (...release, ...barrier)
Clang doesn't have /volatile:ms anymore so we cant rely on that
Assuming MSVC-like or x86 isnt good enough

(and, no retard midwits, volatile is a fine keyword. take ur spec sperging and shove it. i just need to control over-optimization of defacto-weakly ordered access between explicit lockless semaphore yields)
2024-06-23 04:29:21 +01:00
..
Primitives [*] Revert clang 'optimization' because this piece of shit compiler wont listen to me. 2024-05-13 23:43:19 +01:00
Threads [*] Refactor IAuroraThread 2024-05-27 13:28:57 +01:00
AuSleep.cpp [*] i swore i replaced this with a tpause before 2024-05-06 22:47:45 +01:00
AuSleep.hpp [*] Refactoring in progress... 2022-11-17 08:03:20 +00:00
AuWaitFor.cpp [*] YieldPollNs nonzero timeout check 2024-05-27 16:02:54 +01:00
AuWaitFor.hpp [-] Remove 2 year old 0.0 WaitFor back-off implementation 2023-09-12 18:30:45 +01:00
AuWakeInternal.hpp [*] ...and same applies to RWLock 2023-09-09 12:39:47 +01:00
AuWakeOnAddress.cpp [*] Explicit memory order access barrier when reading WOA_SEMAPHORE_MODE-less bAlive under weakly ordered systems. (5b193411 cont: "[*] Improve regressed AuWoA time to wake" 2024-06-23 04:29:21 +01:00
AuWakeOnAddress.hpp [*] Explicit memory order access barrier when reading WOA_SEMAPHORE_MODE-less bAlive under weakly ordered systems. (5b193411 cont: "[*] Improve regressed AuWoA time to wake" 2024-06-23 04:29:21 +01:00