[*] Brute force atomic ordering on foreign architectures
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2e93ca7e32
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@ -350,11 +350,17 @@ template <class T>
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inline auline T AuAtomicUtils<T>::Load(T *in)
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{
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#if defined(AURORA_COMPILER_MSVC) && (defined(AURORA_ARCH_X64) || defined(AURORA_ARCH_X86))
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::_ReadWriteBarrier();
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::_ReadWriteBarrier(); // compile-time only! we use this to prevent optimizations. x86/64 does not care so long as we're aligned.
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return *in;
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#elif defined(AURORA_COMPILER_MSVC)
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::MemoryBarrier(); // works on all legacy MSVC targets including AMD64, IA64, and POWER
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return *in;
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#else
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#if defined(AURORA_COMPILER_CLANG)
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#if !(defined(AURORA_ARCH_X64) || defined(AURORA_ARCH_X86))
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__sync_synchronize(); // brute force on unknown archs. gcc-like compilers will accept this
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#endif
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if constexpr (AuIsSame_v<AuUInt8, T>)
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{
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return ATOMIC_PREFIX_HAX(atomic_load)((atomic_uint_fast8_t *)in, __ATOMIC_ACQUIRE);
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@ -383,7 +389,10 @@ inline auline T AuAtomicUtils<T>::Load(T *in)
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{
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static_assert(AuIsVoid_v<T>, "T");
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}
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#endif
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#else
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return __sync_val_compare_and_swap(*in, 0, 0);
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#endif
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#endif
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}
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template <class T>
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@ -391,9 +400,9 @@ inline auline void AuAtomicUtils<T>::Store(T *in, T val)
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{
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#if defined(AURORA_COMPILER_MSVC) && (defined(AURORA_ARCH_X64) || defined(AURORA_ARCH_X86))
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*in = val;
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::_ReadWriteBarrier();
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#elif defined(AURORA_COMPILER_MSVC)
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*in = val;
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::MemoryBarrier();
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#else
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if constexpr (AuIsSame_v<AuUInt8, T>)
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{
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@ -423,6 +432,9 @@ inline auline void AuAtomicUtils<T>::Store(T *in, T val)
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{
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static_assert(AuIsVoid_v<T>, "T");
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}
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#if !(defined(AURORA_ARCH_X64) || defined(AURORA_ARCH_X86))
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__sync_synchronize();
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#endif
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#endif
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}
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@ -434,9 +446,13 @@ void AuAtomicUtils<AuUInt8>::ClearU8Lock(AuUInt8 *in)
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*in = 0;
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::_ReadWriteBarrier();
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#elif defined(AURORA_COMPILER_MSVC)
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// i think this will work on aarch64 and most risc architectures
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InterlockedAndRelease((volatile LONG *)in, ~0xFF);
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#else
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ATOMIC_PREFIX_HAX(atomic_store)((atomic_uint_fast8_t *)in, 0, __ATOMIC_RELEASE);
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#if !(defined(AURORA_ARCH_X64) || defined(AURORA_ARCH_X86))
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__sync_synchronize();
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#endif
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#endif
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}
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