AuroraMiddleware/SPIRV-Cross
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SPIRV-Cross/reference/shaders/asm/comp/bitcast_iadd.asm.comp

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Implement more correct integer op handling. In some cases we need to bitcast when dealing with int vs. uint. SPIR-V allows inputs to be of different integer signedness, so we need to deal with this somehow. Add testing system to test SPIR-V assembly. For now, test all possible combination for all major cases. - IAdd (which doesn't care about input type as long as they're equal) - SDiv/UDiv operations which case about input type. - Arith/Logical right shifts. - IEqual to test outputs to bvec, which shouldn't get output cast. Also tests casting in function-like calls.
2016-05-10 21:39:41 +00:00
#version 310 es
layout(local_size_x = 1, local_size_y = 1, local_size_z = 1) in;
Fix various corner cases with expression dependencies. There was a potential problem if variables were invalidated and SPIR-V read expressions which depended on other expression which in turn depended on the invalidated variable. Also fixes issue where variables were considered immutable if they were forwardable. This allowed some incorrect optimizations to slip through.
2016-07-12 12:33:04 +00:00
layout(binding = 0, std430) restrict buffer _3
Implement more correct integer op handling. In some cases we need to bitcast when dealing with int vs. uint. SPIR-V allows inputs to be of different integer signedness, so we need to deal with this somehow. Add testing system to test SPIR-V assembly. For now, test all possible combination for all major cases. - IAdd (which doesn't care about input type as long as they're equal) - SDiv/UDiv operations which case about input type. - Arith/Logical right shifts. - IEqual to test outputs to bvec, which shouldn't get output cast. Also tests casting in function-like calls.
2016-05-10 21:39:41 +00:00
{
ivec4 _0;
uvec4 _1;
} _5;
Fix various corner cases with expression dependencies. There was a potential problem if variables were invalidated and SPIR-V read expressions which depended on other expression which in turn depended on the invalidated variable. Also fixes issue where variables were considered immutable if they were forwardable. This allowed some incorrect optimizations to slip through.
2016-07-12 12:33:04 +00:00
layout(binding = 1, std430) restrict buffer _4
Implement more correct integer op handling. In some cases we need to bitcast when dealing with int vs. uint. SPIR-V allows inputs to be of different integer signedness, so we need to deal with this somehow. Add testing system to test SPIR-V assembly. For now, test all possible combination for all major cases. - IAdd (which doesn't care about input type as long as they're equal) - SDiv/UDiv operations which case about input type. - Arith/Logical right shifts. - IEqual to test outputs to bvec, which shouldn't get output cast. Also tests casting in function-like calls.
2016-05-10 21:39:41 +00:00
{
uvec4 _0;
ivec4 _1;
} _6;
void main()
{
Defer parenthesis generation until needed. Previously, we would generate parentheses proactively when generating binary ops, however, this leads to uglier code and hits warnings in compilers when used as a conditional.
2016-12-05 09:22:54 +00:00
_6._0 = _5._1 + uvec4(_5._0);
_6._0 = uvec4(_5._0) + _5._1;
_6._0 = _5._1 + _5._1;
Implement more correct integer op handling. In some cases we need to bitcast when dealing with int vs. uint. SPIR-V allows inputs to be of different integer signedness, so we need to deal with this somehow. Add testing system to test SPIR-V assembly. For now, test all possible combination for all major cases. - IAdd (which doesn't care about input type as long as they're equal) - SDiv/UDiv operations which case about input type. - Arith/Logical right shifts. - IEqual to test outputs to bvec, which shouldn't get output cast. Also tests casting in function-like calls.
2016-05-10 21:39:41 +00:00
_6._0 = uvec4(_5._0 + _5._0);
_6._1 = ivec4(_5._1 + _5._1);
Defer parenthesis generation until needed. Previously, we would generate parentheses proactively when generating binary ops, however, this leads to uglier code and hits warnings in compilers when used as a conditional.
2016-12-05 09:22:54 +00:00
_6._1 = _5._0 + _5._0;
_6._1 = ivec4(_5._1) + _5._0;
_6._1 = _5._0 + ivec4(_5._1);
Implement more correct integer op handling. In some cases we need to bitcast when dealing with int vs. uint. SPIR-V allows inputs to be of different integer signedness, so we need to deal with this somehow. Add testing system to test SPIR-V assembly. For now, test all possible combination for all major cases. - IAdd (which doesn't care about input type as long as they're equal) - SDiv/UDiv operations which case about input type. - Arith/Logical right shifts. - IEqual to test outputs to bvec, which shouldn't get output cast. Also tests casting in function-like calls.
2016-05-10 21:39:41 +00:00
}
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