AuroraMiddleware/SPIRV-Cross
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91b2f34a3d
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3 Commits

Author SHA1 Message Date
Thomas Roughton
91b2f34a3d Update tests to account for all non-entry-point functions being inlined 2019-08-30 09:39:06 +12:00
Hans-Kristian Arntzen
9436cd3036 MSL: Deal with array copies from and to threadgroup. 2019-08-27 13:18:01 +02:00
Hans-Kristian Arntzen
3e584f2c3f Support LUTs in single-function CFGs on Private storage class. 
Fairly common pattern in unoptimized SPIR-V. Support this case as well.
 2019-02-06 10:38:59 +01:00