2024-04-03 11:15:41 +00:00
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/* Double-precision vector (Advanced SIMD) sinh function
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Copyright (C) 2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include "v_math.h"
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#include "poly_advsimd_f64.h"
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static const struct data
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{
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aarch64: Fix AdvSIMD libmvec routines for big-endian
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-02 15:43:13 +00:00
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float64x2_t poly[11], inv_ln2;
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double m_ln2[2];
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float64x2_t shift;
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2024-04-03 11:15:41 +00:00
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uint64x2_t halff;
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int64x2_t onef;
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#if WANT_SIMD_EXCEPT
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uint64x2_t tiny_bound, thresh;
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#else
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uint64x2_t large_bound;
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#endif
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} data = {
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/* Generated using Remez, deg=12 in [-log(2)/2, log(2)/2]. */
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.poly = { V2 (0x1p-1), V2 (0x1.5555555555559p-3), V2 (0x1.555555555554bp-5),
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V2 (0x1.111111110f663p-7), V2 (0x1.6c16c16c1b5f3p-10),
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V2 (0x1.a01a01affa35dp-13), V2 (0x1.a01a018b4ecbbp-16),
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V2 (0x1.71ddf82db5bb4p-19), V2 (0x1.27e517fc0d54bp-22),
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V2 (0x1.af5eedae67435p-26), V2 (0x1.1f143d060a28ap-29), },
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.inv_ln2 = V2 (0x1.71547652b82fep0),
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aarch64: Fix AdvSIMD libmvec routines for big-endian
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-02 15:43:13 +00:00
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.m_ln2 = {-0x1.62e42fefa39efp-1, -0x1.abc9e3b39803fp-56},
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2024-04-03 11:15:41 +00:00
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.shift = V2 (0x1.8p52),
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.halff = V2 (0x3fe0000000000000),
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.onef = V2 (0x3ff0000000000000),
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#if WANT_SIMD_EXCEPT
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/* 2^-26, below which sinh(x) rounds to x. */
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.tiny_bound = V2 (0x3e50000000000000),
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/* asuint(large_bound) - asuint(tiny_bound). */
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.thresh = V2 (0x0230000000000000),
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#else
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/* 2^9. expm1 helper overflows for large input. */
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.large_bound = V2 (0x4080000000000000),
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#endif
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};
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static inline float64x2_t
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expm1_inline (float64x2_t x)
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{
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const struct data *d = ptr_barrier (&data);
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/* Reduce argument:
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exp(x) - 1 = 2^i * (expm1(f) + 1) - 1
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where i = round(x / ln2)
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and f = x - i * ln2 (f in [-ln2/2, ln2/2]). */
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float64x2_t j = vsubq_f64 (vfmaq_f64 (d->shift, d->inv_ln2, x), d->shift);
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int64x2_t i = vcvtq_s64_f64 (j);
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aarch64: Fix AdvSIMD libmvec routines for big-endian
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-02 15:43:13 +00:00
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float64x2_t m_ln2 = vld1q_f64 (d->m_ln2);
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float64x2_t f = vfmaq_laneq_f64 (x, j, m_ln2, 0);
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f = vfmaq_laneq_f64 (f, j, m_ln2, 1);
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/* Approximate expm1(f) using polynomial. */
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float64x2_t f2 = vmulq_f64 (f, f);
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float64x2_t f4 = vmulq_f64 (f2, f2);
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float64x2_t f8 = vmulq_f64 (f4, f4);
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float64x2_t p = vfmaq_f64 (f, f2, v_estrin_10_f64 (f, f2, f4, f8, d->poly));
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/* t = 2^i. */
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float64x2_t t = vreinterpretq_f64_u64 (
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vreinterpretq_u64_s64 (vaddq_s64 (vshlq_n_s64 (i, 52), d->onef)));
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/* expm1(x) ~= p * t + (t - 1). */
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return vfmaq_f64 (vsubq_f64 (t, v_f64 (1.0)), p, t);
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}
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static float64x2_t NOINLINE VPCS_ATTR
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special_case (float64x2_t x)
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{
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return v_call_f64 (sinh, x, x, v_u64 (-1));
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}
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/* Approximation for vector double-precision sinh(x) using expm1.
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sinh(x) = (exp(x) - exp(-x)) / 2.
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The greatest observed error is 2.57 ULP:
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_ZGVnN2v_sinh (0x1.9fb1d49d1d58bp-2) got 0x1.ab34e59d678dcp-2
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want 0x1.ab34e59d678d9p-2. */
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float64x2_t VPCS_ATTR V_NAME_D1 (sinh) (float64x2_t x)
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{
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const struct data *d = ptr_barrier (&data);
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float64x2_t ax = vabsq_f64 (x);
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uint64x2_t sign
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= veorq_u64 (vreinterpretq_u64_f64 (x), vreinterpretq_u64_f64 (ax));
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float64x2_t halfsign = vreinterpretq_f64_u64 (vorrq_u64 (sign, d->halff));
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#if WANT_SIMD_EXCEPT
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uint64x2_t special = vcgeq_u64 (
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vsubq_u64 (vreinterpretq_u64_f64 (ax), d->tiny_bound), d->thresh);
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#else
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uint64x2_t special = vcgeq_u64 (vreinterpretq_u64_f64 (ax), d->large_bound);
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#endif
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/* Fall back to scalar variant for all lanes if any of them are special. */
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if (__glibc_unlikely (v_any_u64 (special)))
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return special_case (x);
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/* Up to the point that expm1 overflows, we can use it to calculate sinh
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using a slight rearrangement of the definition of sinh. This allows us to
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retain acceptable accuracy for very small inputs. */
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float64x2_t t = expm1_inline (ax);
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t = vaddq_f64 (t, vdivq_f64 (t, vaddq_f64 (t, v_f64 (1.0))));
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return vmulq_f64 (t, halfsign);
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}
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