2024-04-03 11:15:41 +00:00
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/* Single-precision inline helper for vector (Advanced SIMD) expm1 function
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Copyright (C) 2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef AARCH64_FPU_V_EXPM1F_INLINE_H
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#define AARCH64_FPU_V_EXPM1F_INLINE_H
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#include "v_math.h"
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#include "poly_advsimd_f32.h"
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struct v_expm1f_data
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{
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float32x4_t poly[5];
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aarch64: Fix AdvSIMD libmvec routines for big-endian
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-02 15:43:13 +00:00
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float invln2_and_ln2[4];
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float32x4_t shift;
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2024-04-03 11:15:41 +00:00
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int32x4_t exponent_bias;
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};
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/* Coefficients generated using fpminimax with degree=5 in [-log(2)/2,
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log(2)/2]. Exponent bias is asuint(1.0f).
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invln2_and_ln2 Stores constants: invln2, ln2_lo, ln2_hi, 0. */
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#define V_EXPM1F_DATA \
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{ \
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.poly = { V4 (0x1.fffffep-2), V4 (0x1.5554aep-3), V4 (0x1.555736p-5), \
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V4 (0x1.12287cp-7), V4 (0x1.6b55a2p-10) }, \
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.shift = V4 (0x1.8p23f), .exponent_bias = V4 (0x3f800000), \
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.invln2_and_ln2 = { 0x1.715476p+0f, 0x1.62e4p-1f, 0x1.7f7d1cp-20f, 0 }, \
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}
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static inline float32x4_t
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expm1f_inline (float32x4_t x, const struct v_expm1f_data *d)
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{
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/* Helper routine for calculating exp(x) - 1.
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Copied from v_expm1f_1u6.c, with all special-case handling removed - the
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calling routine should handle special values if required. */
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/* Reduce argument: f in [-ln2/2, ln2/2], i is exact. */
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aarch64: Fix AdvSIMD libmvec routines for big-endian
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-02 15:43:13 +00:00
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float32x4_t invln2_and_ln2 = vld1q_f32 (d->invln2_and_ln2);
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float32x4_t j
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= vsubq_f32 (vfmaq_laneq_f32 (d->shift, x, invln2_and_ln2, 0), d->shift);
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2024-04-03 11:15:41 +00:00
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int32x4_t i = vcvtq_s32_f32 (j);
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aarch64: Fix AdvSIMD libmvec routines for big-endian
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-02 15:43:13 +00:00
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float32x4_t f = vfmsq_laneq_f32 (x, j, invln2_and_ln2, 1);
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f = vfmsq_laneq_f32 (f, j, invln2_and_ln2, 2);
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2024-04-03 11:15:41 +00:00
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/* Approximate expm1(f) with polynomial P, expm1(f) ~= f + f^2 * P(f).
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Uses Estrin scheme, where the main _ZGVnN4v_expm1f routine uses
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Horner. */
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float32x4_t f2 = vmulq_f32 (f, f);
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float32x4_t f4 = vmulq_f32 (f2, f2);
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float32x4_t p = v_estrin_4_f32 (f, f2, f4, d->poly);
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p = vfmaq_f32 (f, f2, p);
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/* t = 2^i. */
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int32x4_t u = vaddq_s32 (vshlq_n_s32 (i, 23), d->exponent_bias);
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float32x4_t t = vreinterpretq_f32_s32 (u);
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/* expm1(x) ~= p * t + (t - 1). */
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return vfmaq_f32 (vsubq_f32 (t, v_f32 (1.0f)), p, t);
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}
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#endif
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