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Fix whitespaces.
This commit is contained in:
Ulrich Drepper
parent
158db12267
commit
1dc242356a
@ -68,7 +68,7 @@ EALIGN (BP_SYM(memcmp),4,0)
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/* At this point we know both strings have the same alignment and the
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compare length is at least 8 bytes. rBITDIF contains the low order
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2 bits of rSTR1 and cr5 contains the result of the logical compare
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of rBITDIF to 0. If rBITDIF == 0 then we are already word
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of rBITDIF to 0. If rBITDIF == 0 then we are already word
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aligned and can perform the word aligned loop.
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Otherwise we know the two strings have the same alignment (but not
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@ -159,7 +159,7 @@ L(dP1):
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(8-15 byte compare), we want to use only volatile registers. This
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means we can avoid restoring non-volatile registers since we did not
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change any on the early exit path. The key here is the non-early
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exit path only cares about the condition code (cr5), not about which
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exit path only cares about the condition code (cr5), not about which
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register pair was used. */
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lwz rWORD5,0(rSTR1)
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lwz rWORD6,0(rSTR2)
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@ -339,7 +339,7 @@ L(d24):
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bne cr6,L(dLcr6)
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L(d14):
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slwi. r12,rN,3
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bne cr5,L(dLcr5)
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bne cr5,L(dLcr5)
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L(d04):
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lwz r30,44(1)
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lwz r31,48(1)
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@ -348,10 +348,10 @@ L(d04):
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beq L(zeroLength)
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/* At this point we have a remainder of 1 to 3 bytes to compare. Since
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we are aligned it is safe to load the whole word, and use
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shift right to eliminate bits beyond the compare length. */
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shift right to eliminate bits beyond the compare length. */
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L(d00):
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lwz rWORD1,4(rSTR1)
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lwz rWORD2,4(rSTR2)
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lwz rWORD2,4(rSTR2)
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srw rWORD1,rWORD1,rN
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srw rWORD2,rWORD2,rN
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cmplw rWORD1,rWORD2
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@ -406,11 +406,11 @@ L(bytealigned):
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mtctr rN
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/* We need to prime this loop. This loop is swing modulo scheduled
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to avoid pipe delays. The dependent instruction latencies (load to
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to avoid pipe delays. The dependent instruction latencies (load to
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compare to conditional branch) is 2 to 3 cycles. In this loop each
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dispatch group ends in a branch and takes 1 cycle. Effectively
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the first iteration of the loop only serves to load operands and
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branches based on compares are delayed until the next loop.
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the first iteration of the loop only serves to load operands and
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branches based on compares are delayed until the next loop.
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So we must precondition some registers and condition codes so that
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we don't exit the loop early on the first iteration. */
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@ -450,7 +450,7 @@ L(bLoop):
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/* We speculatively loading bytes before we have tested the previous
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bytes. But we must avoid overrunning the length (in the ctr) to
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prevent these speculative loads from causing a segfault. In this
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prevent these speculative loads from causing a segfault. In this
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case the loop will exit early (before the all pending bytes are
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tested. In this case we must complete the pending operations
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before returning. */
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@ -503,7 +503,7 @@ L(bx12):
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sub rRTN,rWORD1,rWORD2
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blr
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.align 4
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.align 4
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L(zeroLengthReturn):
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L(zeroLength):
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@ -515,9 +515,9 @@ L(zeroLength):
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/* At this point we know the strings have different alignment and the
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compare length is at least 8 bytes. rBITDIF contains the low order
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2 bits of rSTR1 and cr5 contains the result of the logical compare
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of rBITDIF to 0. If rBITDIF == 0 then rStr1 is word aligned and can
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of rBITDIF to 0. If rBITDIF == 0 then rStr1 is word aligned and can
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perform the Wunaligned loop.
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Otherwise we know that rSTR1 is not aready word aligned yet.
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So we can force the string addresses to the next lower word
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boundary and special case this first word using shift left to
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@ -554,7 +554,7 @@ L(unaligned):
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stw r26,28(r1)
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cfi_offset(r26,(28-64))
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/* Compute the left/right shift counts for the unalign rSTR2,
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compensating for the logical (W aligned) start of rSTR1. */
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compensating for the logical (W aligned) start of rSTR1. */
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clrlwi rSHL,r27,30
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clrrwi rSTR1,rSTR1,2
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stw r25,24(r1)
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@ -892,9 +892,9 @@ L(du14):
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slwi. rN,rN,3
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bne cr5,L(duLcr5)
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/* At this point we have a remainder of 1 to 3 bytes to compare. We use
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shift right to eliminate bits beyond the compare length.
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shift right to eliminate bits beyond the compare length.
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However it may not be safe to load rWORD2 which may be beyond the
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However it may not be safe to load rWORD2 which may be beyond the
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string length. So we compare the bit length of the remainder to
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the right shift count (rSHR). If the bit count is less than or equal
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we do not need to load rWORD2 (all significant bits are already in
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@ -909,7 +909,7 @@ L(du14):
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L(dutrim):
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lwz rWORD1,4(rSTR1)
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lwz r31,48(1)
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subfic rN,rN,32 /* Shift count is 32 - (rN * 8). */
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subfic rN,rN,32 /* Shift count is 32 - (rN * 8). */
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or rWORD2,rA,rB
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lwz r30,44(1)
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lwz r29,40(r1)
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@ -35,7 +35,7 @@ EALIGN (BP_SYM(strncmp),4,0)
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#define rSTR2 r4 /* second string arg */
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#define rN r5 /* max string length */
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/* Note: The Bounded pointer support in this code is broken. This code
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was inherited from PPC32 and and that support was never completed.
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was inherited from PPC32 and and that support was never completed.
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Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */
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#define rWORD1 r6 /* current word in s1 */
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#define rWORD2 r7 /* current word in s2 */
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@ -35,7 +35,7 @@ EALIGN (BP_SYM(memcmp),4,0)
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#define rSTR2 r4 /* second string arg */
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#define rN r5 /* max string length */
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/* Note: The Bounded pointer support in this code is broken. This code
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was inherited from PPC32 and and that support was never completed.
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was inherited from PPC32 and and that support was never completed.
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Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */
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#define rWORD1 r6 /* current word in s1 */
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#define rWORD2 r7 /* current word in s2 */
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@ -67,9 +67,9 @@ EALIGN (BP_SYM(memcmp),4,0)
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/* At this point we know both strings have the same alignment and the
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compare length is at least 8 bytes. rBITDIF containes the low order
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3 bits of rSTR1 and cr5 contains the result of the logical compare
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of rBITDIF to 0. If rBITDIF == 0 then we are already double word
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of rBITDIF to 0. If rBITDIF == 0 then we are already double word
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aligned and can perform the DWaligned loop.
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Otherwise we know the two strings have the same alignment (but not
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yet DW). So we can force the string addresses to the next lower DW
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boundary and special case this first DW word using shift left to
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@ -158,7 +158,7 @@ L(dP1):
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(8-15 byte compare), we want to use only volitile registers. This
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means we can avoid restoring non-volitile registers since we did not
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change any on the early exit path. The key here is the non-early
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exit path only cares about the condition code (cr5), not about which
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exit path only cares about the condition code (cr5), not about which
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register pair was used. */
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ld rWORD5,0(rSTR1)
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ld rWORD6,0(rSTR2)
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@ -335,7 +335,7 @@ L(d24):
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bne cr6,L(dLcr6)
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L(d14):
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sldi. r12,rN,3
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bne cr5,L(dLcr5)
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bne cr5,L(dLcr5)
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L(d04):
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ld rWORD8,-8(r1)
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ld rWORD7,-16(r1)
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@ -343,10 +343,10 @@ L(d04):
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beq L(zeroLength)
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/* At this point we have a remainder of 1 to 7 bytes to compare. Since
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we are aligned it is safe to load the whole double word, and use
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shift right double to elliminate bits beyond the compare length. */
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shift right double to elliminate bits beyond the compare length. */
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L(d00):
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ld rWORD1,8(rSTR1)
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ld rWORD2,8(rSTR2)
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ld rWORD2,8(rSTR2)
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srd rWORD1,rWORD1,rN
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srd rWORD2,rWORD2,rN
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cmpld cr5,rWORD1,rWORD2
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@ -393,15 +393,15 @@ L(bytealigned):
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beq cr6,L(zeroLength)
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/* We need to prime this loop. This loop is swing modulo scheduled
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to avoid pipe delays. The dependent instruction latencies (load to
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to avoid pipe delays. The dependent instruction latencies (load to
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compare to conditional branch) is 2 to 3 cycles. In this loop each
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dispatch group ends in a branch and takes 1 cycle. Effectively
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the first iteration of the loop only serves to load operands and
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branches based on compares are delayed until the next loop.
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the first iteration of the loop only serves to load operands and
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branches based on compares are delayed until the next loop.
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So we must precondition some registers and condition codes so that
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we don't exit the loop early on the first iteration. */
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lbz rWORD1,0(rSTR1)
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lbz rWORD2,0(rSTR2)
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bdz L(b11)
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@ -438,7 +438,7 @@ L(bLoop):
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/* We speculatively loading bytes before we have tested the previous
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bytes. But we must avoid overrunning the length (in the ctr) to
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prevent these speculative loads from causing a segfault. In this
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prevent these speculative loads from causing a segfault. In this
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case the loop will exit early (before the all pending bytes are
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tested. In this case we must complete the pending operations
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before returning. */
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@ -489,7 +489,7 @@ L(b11):
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L(bx12):
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sub rRTN,rWORD1,rWORD2
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blr
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.align 4
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.align 4
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L(zeroLengthReturn):
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ld rWORD8,-8(r1)
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ld rWORD7,-16(r1)
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@ -501,9 +501,9 @@ L(zeroLength):
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/* At this point we know the strings have different alignment and the
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compare length is at least 8 bytes. rBITDIF containes the low order
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3 bits of rSTR1 and cr5 contains the result of the logical compare
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of rBITDIF to 0. If rBITDIF == 0 then rStr1 is double word
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of rBITDIF to 0. If rBITDIF == 0 then rStr1 is double word
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aligned and can perform the DWunaligned loop.
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Otherwise we know that rSTR1 is not aready DW aligned yet.
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So we can force the string addresses to the next lower DW
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boundary and special case this first DW word using shift left to
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@ -541,7 +541,7 @@ L(unaligned):
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std r26,-48(r1)
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cfi_offset(r26,-48)
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/* Compute the leaft/right shift counts for the unalign rSTR2,
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compensating for the logical (DW aligned) start of rSTR1. */
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compensating for the logical (DW aligned) start of rSTR1. */
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clrldi rSHL,r27,61
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clrrdi rSTR1,rSTR1,3
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std r25,-56(r1)
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@ -879,11 +879,11 @@ L(du14):
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sldi. rN,rN,3
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bne cr5,L(duLcr5)
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/* At this point we have a remainder of 1 to 7 bytes to compare. We use
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shift right double to elliminate bits beyond the compare length.
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shift right double to elliminate bits beyond the compare length.
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This allows the use of double word subtract to compute the final
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result.
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However it may not be safe to load rWORD2 which may be beyond the
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However it may not be safe to load rWORD2 which may be beyond the
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string length. So we compare the bit length of the remainder to
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the right shift count (rSHR). If the bit count is less than or equal
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we do not need to load rWORD2 (all significant bits are already in
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@ -898,7 +898,7 @@ L(du14):
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L(dutrim):
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ld rWORD1,8(rSTR1)
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ld rWORD8,-8(r1)
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subfic rN,rN,64 /* Shift count is 64 - (rN * 8). */
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subfic rN,rN,64 /* Shift count is 64 - (rN * 8). */
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or rWORD2,rA,rB
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ld rWORD7,-16(r1)
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ld r29,-24(r1)
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@ -36,7 +36,7 @@ EALIGN (BP_SYM(strncmp),4,0)
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#define rSTR2 r4 /* second string arg */
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#define rN r5 /* max string length */
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/* Note: The Bounded pointer support in this code is broken. This code
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was inherited from PPC32 and and that support was never completed.
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was inherited from PPC32 and and that support was never completed.
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Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */
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#define rWORD1 r6 /* current word in s1 */
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#define rWORD2 r7 /* current word in s2 */
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