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aarch64: Added optimized memset for A64FX
This patch optimizes the performance of memset for A64FX [1] which implements ARMv8-A SVE and has L1 64KB cache per core and L2 8MB cache per NUMA node. The performance optimization makes use of Scalable Vector Register with several techniques such as loop unrolling, memory access alignment, cache zero fill and prefetch. SVE assembler code for memset is implemented as Vector Length Agnostic code so theoretically it can be run on any SOC which supports ARMv8-A SVE standard. We confirmed that all testcases have been passed by running 'make check' and 'make xcheck' not only on A64FX but also on ThunderX2. And also we confirmed that the SVE 512 bit vector register performance is roughly 4 times better than Advanced SIMD 128 bit register and 8 times better than scalar 64 bit register by running 'make bench'. [1] https://github.com/fujitsu/A64FX Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com> Reviewed-by: Szabolcs Nagy <Szabolcs.Nagy@arm.com>
This commit is contained in:
Naohiro Tamura
Szabolcs Nagy
parent
fa527f345c
commit
4f26956d5b
@ -2,6 +2,7 @@ ifeq ($(subdir),string)
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sysdep_routines += memcpy_generic memcpy_advsimd memcpy_thunderx memcpy_thunderx2 \
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memcpy_falkor memcpy_a64fx \
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memset_generic memset_falkor memset_emag memset_kunpeng \
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memset_a64fx \
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memchr_generic memchr_nosimd \
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strlen_mte strlen_asimd
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endif
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@ -37,7 +37,7 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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INIT_ARCH ();
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/* Support sysdeps/aarch64/multiarch/memcpy.c and memmove.c. */
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/* Support sysdeps/aarch64/multiarch/memcpy.c, memmove.c and memset.c. */
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IFUNC_IMPL (i, name, memcpy,
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IFUNC_IMPL_ADD (array, i, memcpy, 1, __memcpy_thunderx)
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IFUNC_IMPL_ADD (array, i, memcpy, !bti, __memcpy_thunderx2)
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@ -62,6 +62,9 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL_ADD (array, i, memset, (zva_size == 64), __memset_falkor)
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IFUNC_IMPL_ADD (array, i, memset, (zva_size == 64), __memset_emag)
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IFUNC_IMPL_ADD (array, i, memset, 1, __memset_kunpeng)
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#if HAVE_AARCH64_SVE_ASM
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IFUNC_IMPL_ADD (array, i, memset, sve, __memset_a64fx)
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#endif
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IFUNC_IMPL_ADD (array, i, memset, 1, __memset_generic))
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IFUNC_IMPL (i, name, memchr,
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IFUNC_IMPL_ADD (array, i, memchr, !mte, __memchr_nosimd)
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@ -31,16 +31,25 @@ extern __typeof (__redirect_memset) __libc_memset;
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extern __typeof (__redirect_memset) __memset_falkor attribute_hidden;
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extern __typeof (__redirect_memset) __memset_emag attribute_hidden;
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extern __typeof (__redirect_memset) __memset_kunpeng attribute_hidden;
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# if HAVE_AARCH64_SVE_ASM
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extern __typeof (__redirect_memset) __memset_a64fx attribute_hidden;
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# endif
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extern __typeof (__redirect_memset) __memset_generic attribute_hidden;
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libc_ifunc (__libc_memset,
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IS_KUNPENG920 (midr)
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?__memset_kunpeng
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: ((IS_FALKOR (midr) || IS_PHECDA (midr)) && zva_size == 64
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? __memset_falkor
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: (IS_EMAG (midr) && zva_size == 64
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? __memset_emag
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: __memset_generic)));
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? __memset_falkor
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: (IS_EMAG (midr) && zva_size == 64
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? __memset_emag
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# if HAVE_AARCH64_SVE_ASM
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: (IS_A64FX (midr)
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? __memset_a64fx
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: __memset_generic))));
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# else
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: __memset_generic)));
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# endif
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# undef memset
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strong_alias (__libc_memset, memset);
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268
sysdeps/aarch64/multiarch/memset_a64fx.S
Normal file
268
sysdeps/aarch64/multiarch/memset_a64fx.S
Normal file
@ -0,0 +1,268 @@
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/* Optimized memset for Fujitsu A64FX processor.
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Copyright (C) 2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include <sysdeps/aarch64/memset-reg.h>
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/* Assumptions:
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*
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* ARMv8.2-a, AArch64, unaligned accesses, sve
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*
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*/
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#define L1_SIZE (64*1024) // L1 64KB
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#define L2_SIZE (8*1024*1024) // L2 8MB - 1MB
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#define CACHE_LINE_SIZE 256
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#define PF_DIST_L1 (CACHE_LINE_SIZE * 16) // Prefetch distance L1
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#define ZF_DIST (CACHE_LINE_SIZE * 21) // Zerofill distance
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#define rest x8
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#define vector_length x9
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#define vl_remainder x10 // vector_length remainder
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#define cl_remainder x11 // CACHE_LINE_SIZE remainder
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#if HAVE_AARCH64_SVE_ASM
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# if IS_IN (libc)
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# define MEMSET __memset_a64fx
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.arch armv8.2-a+sve
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.macro dc_zva times
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dc zva, tmp1
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add tmp1, tmp1, CACHE_LINE_SIZE
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.if \times-1
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dc_zva "(\times-1)"
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.endif
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.endm
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.macro st1b_unroll first=0, last=7
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st1b z0.b, p0, [dst, #\first, mul vl]
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.if \last-\first
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st1b_unroll "(\first+1)", \last
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.endif
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.endm
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.macro shortcut_for_small_size exit
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// if rest <= vector_length * 2
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whilelo p0.b, xzr, count
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whilelo p1.b, vector_length, count
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b.last 1f
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st1b z0.b, p0, [dstin, #0, mul vl]
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st1b z0.b, p1, [dstin, #1, mul vl]
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ret
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1: // if rest > vector_length * 8
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cmp count, vector_length, lsl 3 // vector_length * 8
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b.hi \exit
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// if rest <= vector_length * 4
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lsl tmp1, vector_length, 1 // vector_length * 2
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whilelo p2.b, tmp1, count
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incb tmp1
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whilelo p3.b, tmp1, count
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b.last 1f
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st1b z0.b, p0, [dstin, #0, mul vl]
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st1b z0.b, p1, [dstin, #1, mul vl]
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st1b z0.b, p2, [dstin, #2, mul vl]
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st1b z0.b, p3, [dstin, #3, mul vl]
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ret
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1: // if rest <= vector_length * 8
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lsl tmp1, vector_length, 2 // vector_length * 4
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whilelo p4.b, tmp1, count
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incb tmp1
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whilelo p5.b, tmp1, count
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b.last 1f
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st1b z0.b, p0, [dstin, #0, mul vl]
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st1b z0.b, p1, [dstin, #1, mul vl]
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st1b z0.b, p2, [dstin, #2, mul vl]
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st1b z0.b, p3, [dstin, #3, mul vl]
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st1b z0.b, p4, [dstin, #4, mul vl]
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st1b z0.b, p5, [dstin, #5, mul vl]
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ret
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1: lsl tmp1, vector_length, 2 // vector_length * 4
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incb tmp1 // vector_length * 5
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incb tmp1 // vector_length * 6
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whilelo p6.b, tmp1, count
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incb tmp1
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whilelo p7.b, tmp1, count
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st1b z0.b, p0, [dstin, #0, mul vl]
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st1b z0.b, p1, [dstin, #1, mul vl]
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st1b z0.b, p2, [dstin, #2, mul vl]
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st1b z0.b, p3, [dstin, #3, mul vl]
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st1b z0.b, p4, [dstin, #4, mul vl]
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st1b z0.b, p5, [dstin, #5, mul vl]
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st1b z0.b, p6, [dstin, #6, mul vl]
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st1b z0.b, p7, [dstin, #7, mul vl]
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ret
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.endm
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ENTRY (MEMSET)
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PTR_ARG (0)
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SIZE_ARG (2)
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cbnz count, 1f
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ret
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1: dup z0.b, valw
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cntb vector_length
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// shortcut for less than vector_length * 8
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// gives a free ptrue to p0.b for n >= vector_length
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shortcut_for_small_size L(vl_agnostic)
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// end of shortcut
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L(vl_agnostic): // VL Agnostic
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mov rest, count
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mov dst, dstin
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add dstend, dstin, count
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// if rest >= L2_SIZE && vector_length == 64 then L(L2)
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mov tmp1, 64
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cmp rest, L2_SIZE
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ccmp vector_length, tmp1, 0, cs
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b.eq L(L2)
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// if rest >= L1_SIZE && vector_length == 64 then L(L1_prefetch)
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cmp rest, L1_SIZE
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ccmp vector_length, tmp1, 0, cs
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b.eq L(L1_prefetch)
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L(unroll32):
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lsl tmp1, vector_length, 3 // vector_length * 8
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lsl tmp2, vector_length, 5 // vector_length * 32
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.p2align 3
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1: cmp rest, tmp2
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b.cc L(unroll8)
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st1b_unroll
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add dst, dst, tmp1
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st1b_unroll
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add dst, dst, tmp1
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st1b_unroll
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add dst, dst, tmp1
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st1b_unroll
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add dst, dst, tmp1
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sub rest, rest, tmp2
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b 1b
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L(unroll8):
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lsl tmp1, vector_length, 3
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.p2align 3
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1: cmp rest, tmp1
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b.cc L(last)
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st1b_unroll
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add dst, dst, tmp1
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sub rest, rest, tmp1
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b 1b
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L(last):
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whilelo p0.b, xzr, rest
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whilelo p1.b, vector_length, rest
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b.last 1f
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st1b z0.b, p0, [dst, #0, mul vl]
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st1b z0.b, p1, [dst, #1, mul vl]
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ret
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1: lsl tmp1, vector_length, 1 // vector_length * 2
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whilelo p2.b, tmp1, rest
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incb tmp1
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whilelo p3.b, tmp1, rest
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b.last 1f
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st1b z0.b, p0, [dst, #0, mul vl]
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st1b z0.b, p1, [dst, #1, mul vl]
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st1b z0.b, p2, [dst, #2, mul vl]
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st1b z0.b, p3, [dst, #3, mul vl]
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ret
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1: lsl tmp1, vector_length, 2 // vector_length * 4
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whilelo p4.b, tmp1, rest
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incb tmp1
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whilelo p5.b, tmp1, rest
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incb tmp1
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whilelo p6.b, tmp1, rest
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incb tmp1
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whilelo p7.b, tmp1, rest
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st1b z0.b, p0, [dst, #0, mul vl]
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st1b z0.b, p1, [dst, #1, mul vl]
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st1b z0.b, p2, [dst, #2, mul vl]
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st1b z0.b, p3, [dst, #3, mul vl]
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st1b z0.b, p4, [dst, #4, mul vl]
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st1b z0.b, p5, [dst, #5, mul vl]
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st1b z0.b, p6, [dst, #6, mul vl]
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st1b z0.b, p7, [dst, #7, mul vl]
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ret
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L(L1_prefetch): // if rest >= L1_SIZE
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.p2align 3
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1: st1b_unroll 0, 3
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prfm pstl1keep, [dst, PF_DIST_L1]
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st1b_unroll 4, 7
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prfm pstl1keep, [dst, PF_DIST_L1 + CACHE_LINE_SIZE]
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add dst, dst, CACHE_LINE_SIZE * 2
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sub rest, rest, CACHE_LINE_SIZE * 2
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cmp rest, L1_SIZE
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b.ge 1b
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cbnz rest, L(unroll32)
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ret
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L(L2):
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// align dst address at vector_length byte boundary
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sub tmp1, vector_length, 1
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ands tmp2, dst, tmp1
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// if vl_remainder == 0
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b.eq 1f
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sub vl_remainder, vector_length, tmp2
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// process remainder until the first vector_length boundary
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whilelt p2.b, xzr, vl_remainder
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st1b z0.b, p2, [dst]
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add dst, dst, vl_remainder
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sub rest, rest, vl_remainder
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// align dstin address at CACHE_LINE_SIZE byte boundary
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1: mov tmp1, CACHE_LINE_SIZE
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ands tmp2, dst, CACHE_LINE_SIZE - 1
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// if cl_remainder == 0
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b.eq L(L2_dc_zva)
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sub cl_remainder, tmp1, tmp2
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// process remainder until the first CACHE_LINE_SIZE boundary
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mov tmp1, xzr // index
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2: whilelt p2.b, tmp1, cl_remainder
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st1b z0.b, p2, [dst, tmp1]
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incb tmp1
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cmp tmp1, cl_remainder
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b.lo 2b
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add dst, dst, cl_remainder
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sub rest, rest, cl_remainder
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L(L2_dc_zva):
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// zero fill
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mov tmp1, dst
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dc_zva (ZF_DIST / CACHE_LINE_SIZE) - 1
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mov zva_len, ZF_DIST
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add tmp1, zva_len, CACHE_LINE_SIZE * 2
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// unroll
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.p2align 3
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1: st1b_unroll 0, 3
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add tmp2, dst, zva_len
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dc zva, tmp2
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st1b_unroll 4, 7
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add tmp2, tmp2, CACHE_LINE_SIZE
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dc zva, tmp2
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add dst, dst, CACHE_LINE_SIZE * 2
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sub rest, rest, CACHE_LINE_SIZE * 2
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cmp rest, tmp1 // ZF_DIST + CACHE_LINE_SIZE * 2
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b.ge 1b
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cbnz rest, L(unroll8)
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ret
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END (MEMSET)
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libc_hidden_builtin_def (MEMSET)
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#endif /* IS_IN (libc) */
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#endif /* HAVE_AARCH64_SVE_ASM */
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