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Remove pre-GCC-4.9 MIPS code.
This patch removes some MIPS code in glibc that was conditional on old GCC versions no longer supported for building glibc. Tested with build-many-glibcs.py. * sysdeps/mips/atomic-machine.h (R10K_BEQZ_INSN): Remove. [__GNUC_PREREQ (4, 8) || __mips16]: Make code unconditional. [!__GNUC_PREREQ (4, 8) && !__mips16]: Remove conditional code. * sysdeps/mips/math-tests.h [_MIPS_SIM != _ABIO32 && !__GNUC_PREREQ (4, 9)]: Remove conditional code.
This commit is contained in:
Joseph Myers
parent
37e9dc8146
commit
6c2ec6677b
@ -1,3 +1,12 @@
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2017-06-19 Joseph Myers <joseph@codesourcery.com>
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* sysdeps/mips/atomic-machine.h (R10K_BEQZ_INSN): Remove.
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[__GNUC_PREREQ (4, 8) || __mips16]: Make code unconditional.
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[!__GNUC_PREREQ (4, 8) && !__mips16]: Remove conditional code.
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* sysdeps/mips/math-tests.h
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[_MIPS_SIM != _ABIO32 && !__GNUC_PREREQ (4, 9)]: Remove
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conditional code.
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2017-06-19 Florian Weimer <fweimer@redhat.com>
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* intl/dcigettext.c (DCIGETTEXT): Do not make copy of localename.
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@ -55,76 +55,43 @@ typedef uintmax_t uatomic_max_t;
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# define MIPS_SYNC sync
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#endif
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/* Certain revisions of the R10000 Processor need an LL/SC Workaround
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enabled. Revisions before 3.0 misbehave on atomic operations, and
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Revs 2.6 and lower deadlock after several seconds due to other errata.
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To quote the R10K Errata:
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Workaround: The basic idea is to inhibit the four instructions
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from simultaneously becoming active in R10000. Padding all
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ll/sc sequences with nops or changing the looping branch in the
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routines to a branch likely (which is always predicted taken
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by R10000) will work. The nops should go after the loop, and the
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number of them should be 28. This number could be decremented for
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each additional instruction in the ll/sc loop such as the lock
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modifier(s) between the ll and sc, the looping branch and its
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delay slot. For typical short routines with one ll/sc loop, any
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instructions after the loop could also count as a decrement. The
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nop workaround pollutes the cache more but would be a few cycles
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faster if all the code is in the cache and the looping branch
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is predicted not taken. */
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#ifdef _MIPS_ARCH_R10000
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#define R10K_BEQZ_INSN "beqzl"
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#else
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#define R10K_BEQZ_INSN "beqz"
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#endif
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#define MIPS_SYNC_STR_2(X) #X
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#define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X)
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#define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC)
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#if __GNUC_PREREQ (4, 8) || defined __mips16
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/* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS
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support for their efficient implementation was added only in GCC 4.8.
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We still want to use them even with GCC 4.7 for MIPS16 code where we
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have no assembly alternative available and want to avoid the __sync_*
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builtins if at all possible. */
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# define USE_ATOMIC_COMPILER_BUILTINS 1
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#define USE_ATOMIC_COMPILER_BUILTINS 1
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/* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange
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instruction which will be used by __atomic_exchange_n. */
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# ifdef _MIPS_ARCH_XLP
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# define ATOMIC_EXCHANGE_USES_CAS 0
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# else
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# define ATOMIC_EXCHANGE_USES_CAS 1
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# endif
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#ifdef _MIPS_ARCH_XLP
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# define ATOMIC_EXCHANGE_USES_CAS 0
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#else
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# define ATOMIC_EXCHANGE_USES_CAS 1
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#endif
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/* Compare and exchange.
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For all "bool" routines, we return FALSE if exchange succesful. */
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# define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \
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#define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \
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(abort (), 0)
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# define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \
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#define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \
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(abort (), 0)
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# define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \
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#define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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!__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
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model, __ATOMIC_RELAXED); \
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})
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# define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \
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#define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \
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(abort (), (typeof(*mem)) 0)
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# define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \
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#define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \
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(abort (), (typeof(*mem)) 0)
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# define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \
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#define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
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@ -132,336 +99,91 @@ typedef uintmax_t uatomic_max_t;
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__oldval; \
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})
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# if _MIPS_SIM == _ABIO32
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#if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
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# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
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(abort (), 0)
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# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
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# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
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(abort (), (typeof(*mem)) 0)
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# else
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# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
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#else
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# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
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__arch_compare_and_exchange_bool_32_int (mem, newval, oldval, model)
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# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
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# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
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__arch_compare_and_exchange_val_32_int (mem, newval, oldval, model)
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# endif
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#endif
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/* Compare and exchange with "acquire" semantics, ie barrier after. */
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# define atomic_compare_and_exchange_bool_acq(mem, new, old) \
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#define atomic_compare_and_exchange_bool_acq(mem, new, old) \
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__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
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mem, new, old, __ATOMIC_ACQUIRE)
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# define atomic_compare_and_exchange_val_acq(mem, new, old) \
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#define atomic_compare_and_exchange_val_acq(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, __ATOMIC_ACQUIRE)
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/* Compare and exchange with "release" semantics, ie barrier before. */
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# define atomic_compare_and_exchange_val_rel(mem, new, old) \
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#define atomic_compare_and_exchange_val_rel(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, __ATOMIC_RELEASE)
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/* Atomic exchange (without compare). */
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# define __arch_exchange_8_int(mem, newval, model) \
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#define __arch_exchange_8_int(mem, newval, model) \
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(abort (), (typeof(*mem)) 0)
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# define __arch_exchange_16_int(mem, newval, model) \
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#define __arch_exchange_16_int(mem, newval, model) \
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(abort (), (typeof(*mem)) 0)
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# define __arch_exchange_32_int(mem, newval, model) \
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#define __arch_exchange_32_int(mem, newval, model) \
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__atomic_exchange_n (mem, newval, model)
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# if _MIPS_SIM == _ABIO32
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#if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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# define __arch_exchange_64_int(mem, newval, model) \
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# define __arch_exchange_64_int(mem, newval, model) \
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(abort (), (typeof(*mem)) 0)
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# else
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# define __arch_exchange_64_int(mem, newval, model) \
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#else
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# define __arch_exchange_64_int(mem, newval, model) \
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__atomic_exchange_n (mem, newval, model)
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# endif
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#endif
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# define atomic_exchange_acq(mem, value) \
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#define atomic_exchange_acq(mem, value) \
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__atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE)
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# define atomic_exchange_rel(mem, value) \
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#define atomic_exchange_rel(mem, value) \
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__atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_RELEASE)
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/* Atomically add value and return the previous (unincremented) value. */
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# define __arch_exchange_and_add_8_int(mem, value, model) \
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#define __arch_exchange_and_add_8_int(mem, value, model) \
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(abort (), (typeof(*mem)) 0)
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# define __arch_exchange_and_add_16_int(mem, value, model) \
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#define __arch_exchange_and_add_16_int(mem, value, model) \
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(abort (), (typeof(*mem)) 0)
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# define __arch_exchange_and_add_32_int(mem, value, model) \
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#define __arch_exchange_and_add_32_int(mem, value, model) \
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__atomic_fetch_add (mem, value, model)
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# if _MIPS_SIM == _ABIO32
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#if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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# define __arch_exchange_and_add_64_int(mem, value, model) \
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# define __arch_exchange_and_add_64_int(mem, value, model) \
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(abort (), (typeof(*mem)) 0)
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# else
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# define __arch_exchange_and_add_64_int(mem, value, model) \
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#else
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# define __arch_exchange_and_add_64_int(mem, value, model) \
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__atomic_fetch_add (mem, value, model)
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# endif
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#endif
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# define atomic_exchange_and_add_acq(mem, value) \
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#define atomic_exchange_and_add_acq(mem, value) \
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__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
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__ATOMIC_ACQUIRE)
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# define atomic_exchange_and_add_rel(mem, value) \
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#define atomic_exchange_and_add_rel(mem, value) \
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__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
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__ATOMIC_RELEASE)
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#else /* !__mips16 && !__GNUC_PREREQ (4, 8) */
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/* This implementation using inline assembly will be removed once glibc
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requires GCC 4.8 or later to build. */
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# define USE_ATOMIC_COMPILER_BUILTINS 0
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# define ATOMIC_EXCHANGE_USES_CAS 1
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/* Compare and exchange. For all of the "xxx" routines, we expect a
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"__prev" and a "__cmp" variable to be provided by the enclosing scope,
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in which values are returned. */
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# define __arch_compare_and_exchange_xxx_8_int(mem, newval, oldval, rel, acq) \
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(abort (), __prev = 0, __cmp = 0, (void) __cmp)
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# define __arch_compare_and_exchange_xxx_16_int(mem, newval, oldval, rel, acq) \
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(abort (), __prev = 0, __cmp = 0, (void) __cmp)
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# define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, acq) \
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__asm__ __volatile__ ( \
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".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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rel "\n" \
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"1:\t" \
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"ll %0,%5\n\t" \
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"move %1,$0\n\t" \
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"bne %0,%3,2f\n\t" \
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"move %1,%4\n\t" \
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"sc %1,%2\n\t" \
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R10K_BEQZ_INSN" %1,1b\n" \
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acq "\n\t" \
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".set pop\n" \
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"2:\n\t" \
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: "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \
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: "r" (oldval), "r" (newval), "m" (*mem) \
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: "memory")
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# if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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# define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
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(abort (), __prev = 0, __cmp = 0, (void) __cmp)
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# else
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# define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
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__asm__ __volatile__ ("\n" \
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".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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rel "\n" \
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"1:\t" \
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"lld %0,%5\n\t" \
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"move %1,$0\n\t" \
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"bne %0,%3,2f\n\t" \
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"move %1,%4\n\t" \
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"scd %1,%2\n\t" \
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R10K_BEQZ_INSN" %1,1b\n" \
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acq "\n\t" \
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".set pop\n" \
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"2:\n\t" \
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: "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \
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: "r" (oldval), "r" (newval), "m" (*mem) \
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: "memory")
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# endif
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/* For all "bool" routines, we return FALSE if exchange succesful. */
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# define __arch_compare_and_exchange_bool_8_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp; \
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__arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \
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!__cmp; })
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# define __arch_compare_and_exchange_bool_16_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp; \
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__arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \
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!__cmp; })
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# define __arch_compare_and_exchange_bool_32_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp; \
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__arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \
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!__cmp; })
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# define __arch_compare_and_exchange_bool_64_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp; \
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__arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \
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!__cmp; })
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/* For all "val" routines, return the old value whether exchange
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successful or not. */
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# define __arch_compare_and_exchange_val_8_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \
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(typeof (*mem))__prev; })
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# define __arch_compare_and_exchange_val_16_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \
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(typeof (*mem))__prev; })
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# define __arch_compare_and_exchange_val_32_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \
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(typeof (*mem))__prev; })
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# define __arch_compare_and_exchange_val_64_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \
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(typeof (*mem))__prev; })
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/* Compare and exchange with "acquire" semantics, ie barrier after. */
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# define atomic_compare_and_exchange_bool_acq(mem, new, old) \
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__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
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mem, new, old, "", MIPS_SYNC_STR)
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# define atomic_compare_and_exchange_val_acq(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, "", MIPS_SYNC_STR)
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/* Compare and exchange with "release" semantics, ie barrier before. */
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# define atomic_compare_and_exchange_val_rel(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, MIPS_SYNC_STR, "")
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/* Atomic exchange (without compare). */
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# define __arch_exchange_xxx_8_int(mem, newval, rel, acq) \
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(abort (), (typeof(*mem)) 0)
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# define __arch_exchange_xxx_16_int(mem, newval, rel, acq) \
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(abort (), (typeof(*mem)) 0)
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# define __arch_exchange_xxx_32_int(mem, newval, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__asm__ __volatile__ ("\n" \
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".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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rel "\n" \
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"1:\t" \
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"ll %0,%4\n\t" \
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"move %1,%3\n\t" \
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"sc %1,%2\n\t" \
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R10K_BEQZ_INSN" %1,1b\n" \
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acq "\n\t" \
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".set pop\n" \
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"2:\n\t" \
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: "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \
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: "r" (newval), "m" (*mem) \
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: "memory"); \
|
||||
__prev; })
|
||||
|
||||
# if _MIPS_SIM == _ABIO32
|
||||
/* We can't do an atomic 64-bit operation in O32. */
|
||||
# define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
|
||||
(abort (), (typeof(*mem)) 0)
|
||||
# else
|
||||
# define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
|
||||
({ typeof (*mem) __prev; int __cmp; \
|
||||
__asm__ __volatile__ ("\n" \
|
||||
".set push\n\t" \
|
||||
MIPS_PUSH_MIPS2 \
|
||||
rel "\n" \
|
||||
"1:\n" \
|
||||
"lld %0,%4\n\t" \
|
||||
"move %1,%3\n\t" \
|
||||
"scd %1,%2\n\t" \
|
||||
R10K_BEQZ_INSN" %1,1b\n" \
|
||||
acq "\n\t" \
|
||||
".set pop\n" \
|
||||
"2:\n\t" \
|
||||
: "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \
|
||||
: "r" (newval), "m" (*mem) \
|
||||
: "memory"); \
|
||||
__prev; })
|
||||
# endif
|
||||
|
||||
# define atomic_exchange_acq(mem, value) \
|
||||
__atomic_val_bysize (__arch_exchange_xxx, int, mem, value, "", MIPS_SYNC_STR)
|
||||
|
||||
# define atomic_exchange_rel(mem, value) \
|
||||
__atomic_val_bysize (__arch_exchange_xxx, int, mem, value, MIPS_SYNC_STR, "")
|
||||
|
||||
|
||||
/* Atomically add value and return the previous (unincremented) value. */
|
||||
|
||||
# define __arch_exchange_and_add_8_int(mem, newval, rel, acq) \
|
||||
(abort (), (typeof(*mem)) 0)
|
||||
|
||||
# define __arch_exchange_and_add_16_int(mem, newval, rel, acq) \
|
||||
(abort (), (typeof(*mem)) 0)
|
||||
|
||||
# define __arch_exchange_and_add_32_int(mem, value, rel, acq) \
|
||||
({ typeof (*mem) __prev; int __cmp; \
|
||||
__asm__ __volatile__ ("\n" \
|
||||
".set push\n\t" \
|
||||
MIPS_PUSH_MIPS2 \
|
||||
rel "\n" \
|
||||
"1:\t" \
|
||||
"ll %0,%4\n\t" \
|
||||
"addu %1,%0,%3\n\t" \
|
||||
"sc %1,%2\n\t" \
|
||||
R10K_BEQZ_INSN" %1,1b\n" \
|
||||
acq "\n\t" \
|
||||
".set pop\n" \
|
||||
"2:\n\t" \
|
||||
: "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \
|
||||
: "r" (value), "m" (*mem) \
|
||||
: "memory"); \
|
||||
__prev; })
|
||||
|
||||
# if _MIPS_SIM == _ABIO32
|
||||
/* We can't do an atomic 64-bit operation in O32. */
|
||||
# define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
|
||||
(abort (), (typeof(*mem)) 0)
|
||||
# else
|
||||
# define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
|
||||
({ typeof (*mem) __prev; int __cmp; \
|
||||
__asm__ __volatile__ ( \
|
||||
".set push\n\t" \
|
||||
MIPS_PUSH_MIPS2 \
|
||||
rel "\n" \
|
||||
"1:\t" \
|
||||
"lld %0,%4\n\t" \
|
||||
"daddu %1,%0,%3\n\t" \
|
||||
"scd %1,%2\n\t" \
|
||||
R10K_BEQZ_INSN" %1,1b\n" \
|
||||
acq "\n\t" \
|
||||
".set pop\n" \
|
||||
"2:\n\t" \
|
||||
: "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \
|
||||
: "r" (value), "m" (*mem) \
|
||||
: "memory"); \
|
||||
__prev; })
|
||||
# endif
|
||||
|
||||
# define atomic_exchange_and_add_acq(mem, value) \
|
||||
__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
|
||||
"", MIPS_SYNC_STR)
|
||||
|
||||
# define atomic_exchange_and_add_rel(mem, value) \
|
||||
__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
|
||||
MIPS_SYNC_STR, "")
|
||||
|
||||
#endif /* !__mips16 && !__GNUC_PREREQ (4, 8) */
|
||||
|
||||
/* TODO: More atomic operations could be implemented efficiently; only the
|
||||
basic requirements are done. */
|
||||
|
||||
|
||||
@ -19,10 +19,7 @@
|
||||
#include <features.h>
|
||||
#include <sgidefs.h>
|
||||
|
||||
/* MIPS soft float does not support exceptions and rounding modes, and
|
||||
before GCC 4.9 long double when wider than double is implemented
|
||||
using fp-bit which does not integrate with hardware exceptions and
|
||||
rounding modes. */
|
||||
/* MIPS soft float does not support exceptions and rounding modes. */
|
||||
#ifdef __mips_soft_float
|
||||
# define ROUNDING_TESTS_float(MODE) ((MODE) == FE_TONEAREST)
|
||||
# define ROUNDING_TESTS_double(MODE) ((MODE) == FE_TONEAREST)
|
||||
@ -30,9 +27,6 @@
|
||||
# define EXCEPTION_TESTS_float 0
|
||||
# define EXCEPTION_TESTS_double 0
|
||||
# define EXCEPTION_TESTS_long_double 0
|
||||
#elif _MIPS_SIM != _ABIO32 && !__GNUC_PREREQ (4, 9)
|
||||
# define ROUNDING_TESTS_long_double(MODE) ((MODE) == FE_TONEAREST)
|
||||
# define EXCEPTION_TESTS_long_double 0
|
||||
#endif
|
||||
|
||||
/* NaN payload preservation when converting a signaling NaN to quiet
|
||||
|
||||
Loading…
Reference in New Issue
Block a user