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6c2ec6677b
This patch removes some MIPS code in glibc that was conditional on old GCC versions no longer supported for building glibc. Tested with build-many-glibcs.py. * sysdeps/mips/atomic-machine.h (R10K_BEQZ_INSN): Remove. [__GNUC_PREREQ (4, 8) || __mips16]: Make code unconditional. [!__GNUC_PREREQ (4, 8) && !__mips16]: Remove conditional code. * sysdeps/mips/math-tests.h [_MIPS_SIM != _ABIO32 && !__GNUC_PREREQ (4, 9)]: Remove conditional code.
202 lines
6.5 KiB
C
202 lines
6.5 KiB
C
/* Low-level functions for atomic operations. Mips version.
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Copyright (C) 2005-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _MIPS_ATOMIC_MACHINE_H
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#define _MIPS_ATOMIC_MACHINE_H 1
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#include <stdint.h>
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#include <inttypes.h>
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#include <sgidefs.h>
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typedef int32_t atomic32_t;
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typedef uint32_t uatomic32_t;
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typedef int_fast32_t atomic_fast32_t;
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typedef uint_fast32_t uatomic_fast32_t;
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typedef int64_t atomic64_t;
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typedef uint64_t uatomic64_t;
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typedef int_fast64_t atomic_fast64_t;
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typedef uint_fast64_t uatomic_fast64_t;
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typedef intptr_t atomicptr_t;
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typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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#if _MIPS_SIM == _ABIO32 && __mips < 2
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#define MIPS_PUSH_MIPS2 ".set mips2\n\t"
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#else
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#define MIPS_PUSH_MIPS2
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#endif
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#if _MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIN32
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#define __HAVE_64B_ATOMICS 0
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#else
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#define __HAVE_64B_ATOMICS 1
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#endif
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/* See the comments in <sys/asm.h> about the use of the sync instruction. */
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#ifndef MIPS_SYNC
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# define MIPS_SYNC sync
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#endif
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#define MIPS_SYNC_STR_2(X) #X
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#define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X)
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#define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC)
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#define USE_ATOMIC_COMPILER_BUILTINS 1
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/* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange
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instruction which will be used by __atomic_exchange_n. */
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#ifdef _MIPS_ARCH_XLP
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# define ATOMIC_EXCHANGE_USES_CAS 0
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#else
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# define ATOMIC_EXCHANGE_USES_CAS 1
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#endif
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/* Compare and exchange.
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For all "bool" routines, we return FALSE if exchange succesful. */
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#define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \
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(abort (), 0)
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#define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \
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(abort (), 0)
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#define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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!__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
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model, __ATOMIC_RELAXED); \
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})
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#define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \
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(abort (), (typeof(*mem)) 0)
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#define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \
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(abort (), (typeof(*mem)) 0)
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#define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
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model, __ATOMIC_RELAXED); \
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__oldval; \
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})
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#if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
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(abort (), 0)
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# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
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(abort (), (typeof(*mem)) 0)
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#else
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# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
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__arch_compare_and_exchange_bool_32_int (mem, newval, oldval, model)
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# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
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__arch_compare_and_exchange_val_32_int (mem, newval, oldval, model)
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#endif
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/* Compare and exchange with "acquire" semantics, ie barrier after. */
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#define atomic_compare_and_exchange_bool_acq(mem, new, old) \
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__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
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mem, new, old, __ATOMIC_ACQUIRE)
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#define atomic_compare_and_exchange_val_acq(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, __ATOMIC_ACQUIRE)
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/* Compare and exchange with "release" semantics, ie barrier before. */
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#define atomic_compare_and_exchange_val_rel(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, __ATOMIC_RELEASE)
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/* Atomic exchange (without compare). */
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#define __arch_exchange_8_int(mem, newval, model) \
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(abort (), (typeof(*mem)) 0)
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#define __arch_exchange_16_int(mem, newval, model) \
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(abort (), (typeof(*mem)) 0)
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#define __arch_exchange_32_int(mem, newval, model) \
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__atomic_exchange_n (mem, newval, model)
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#if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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# define __arch_exchange_64_int(mem, newval, model) \
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(abort (), (typeof(*mem)) 0)
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#else
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# define __arch_exchange_64_int(mem, newval, model) \
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__atomic_exchange_n (mem, newval, model)
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#endif
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#define atomic_exchange_acq(mem, value) \
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__atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE)
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#define atomic_exchange_rel(mem, value) \
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__atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_RELEASE)
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/* Atomically add value and return the previous (unincremented) value. */
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#define __arch_exchange_and_add_8_int(mem, value, model) \
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(abort (), (typeof(*mem)) 0)
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#define __arch_exchange_and_add_16_int(mem, value, model) \
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(abort (), (typeof(*mem)) 0)
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#define __arch_exchange_and_add_32_int(mem, value, model) \
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__atomic_fetch_add (mem, value, model)
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#if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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# define __arch_exchange_and_add_64_int(mem, value, model) \
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(abort (), (typeof(*mem)) 0)
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#else
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# define __arch_exchange_and_add_64_int(mem, value, model) \
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__atomic_fetch_add (mem, value, model)
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#endif
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#define atomic_exchange_and_add_acq(mem, value) \
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__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
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__ATOMIC_ACQUIRE)
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#define atomic_exchange_and_add_rel(mem, value) \
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__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
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__ATOMIC_RELEASE)
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/* TODO: More atomic operations could be implemented efficiently; only the
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basic requirements are done. */
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#ifdef __mips16
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# define atomic_full_barrier() __sync_synchronize ()
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#else /* !__mips16 */
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# define atomic_full_barrier() \
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__asm__ __volatile__ (".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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MIPS_SYNC_STR "\n\t" \
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".set pop" : : : "memory")
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#endif /* !__mips16 */
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#endif /* atomic-machine.h */
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