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ARM: soft-fp NaN representation correction

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Commit 7d92b78723 [Fix ARM NAN fraction
bits.] removed all the bits set from NANFRAC macros and, when propagated
to libgcc, regressed gcc.dg/torture/builtin-math-7.c on soft-fp arm-eabi
targets, currently ARMv6-M (`-march=armv6-m -mthumb') only.  This is
because when used to construct a NaN in the semi-raw mode, they now
build an infinity instead.  Consequently operations such as (Inf - Inf)
now produce Inf rather than NaN.  The change worked for the original
test case, posted with PR libgcc/60166, because division is made in the
canonical mode, where the quiet bit is set separately, from the fp
class.

This change brings the quiet bit back to these macros, making semi-raw
mode calculations produce the expected results again.
This commit is contained in:
Maciej W. Rozycki 2014-05-16 22:46:53 +01:00
parent 79520f4bd6
commit deb0f7f6a8
2 changed files with 9 additions and 3 deletions
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6
ChangeLog
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@ -1,3 +1,9 @@
2014-05-16 Maciej W. Rozycki <macro@codesourcery.com>
PR libgcc/60166
* sysdeps/arm/soft-fp/sfp-machine.h (_FP_NANFRAC_S, _FP_NANFRAC_D)
(_FP_NANSIGN_Q): Set the quiet bit.
2014-05-16 Joseph Myers <joseph@codesourcery.com>
* benchtests/Makefile

6
sysdeps/arm/soft-fp/sfp-machine.h
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@ -21,9 +21,9 @@
#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
#define _FP_NANFRAC_S 0
#define _FP_NANFRAC_D 0, 0
#define _FP_NANFRAC_Q 0, 0, 0, 0
#define _FP_NANFRAC_S _FP_QNANBIT_S
#define _FP_NANFRAC_D _FP_QNANBIT_D, 0
#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0
#define _FP_NANSIGN_S 0
#define _FP_NANSIGN_D 0
#define _FP_NANSIGN_Q 0