AuroraMiddleware/glibc
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3 Commits

Author SHA1 Message Date
Ulrich Drepper
8c1dcd265d * sysdeps/x86_64/cacheinfo.c (intel_02_known): Add new entries. 
* sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_known): Likewise.
 2007-07-09 16:12:05 +00:00
Ulrich Drepper
6d59823c29 * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Pass correct value 
as second parameter to handle_intel.
 2007-05-21 22:38:06 +00:00
Ulrich Drepper
bfe6f5fa89 * sysdeps/unix/sysv/linux/x86_64/sysconf.c: Move cache information 
handling to ...
	* sysdeps/x86_64/cacheinfo.c: ... here.  New file.
	* sysdeps/x86_64/Makefile [subdir=string] (sysdep_routines): Add
	cacheinfo.
	* sysdeps/x86_64/memcpy.S: Complete rewrite.
	* sysdeps/x86_64/mempcpy.S: Adjust appropriately.
	Patch by Evandro Menezes <evandro.menezes@amd.com>.

	* sysdeps/unix/sysv/linux/i386/epoll_pwait.S: New file.
 2007-05-21 19:21:48 +00:00