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505 lines
14 KiB
ArmAsm
505 lines
14 KiB
ArmAsm
/* memcmp/wmemcmp optimized with 256-bit EVEX instructions.
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Copyright (C) 2021-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <isa-level.h>
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#if ISA_SHOULD_BUILD (4)
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/* memcmp/wmemcmp is implemented as:
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1. Use ymm vector compares when possible. The only case where
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vector compares is not possible for when size < CHAR_PER_VEC
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and loading from either s1 or s2 would cause a page cross.
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2. For size from 2 to 7 bytes on page cross, load as big endian
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with movbe and bswap to avoid branches.
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3. Use xmm vector compare when size >= 4 bytes for memcmp or
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size >= 8 bytes for wmemcmp.
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4. Optimistically compare up to first 4 * CHAR_PER_VEC one at a
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to check for early mismatches. Only do this if its guaranteed the
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work is not wasted.
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5. If size is 8 * VEC_SIZE or less, unroll the loop.
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6. Compare 4 * VEC_SIZE at a time with the aligned first memory
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area.
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7. Use 2 vector compares when size is 2 * CHAR_PER_VEC or less.
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8. Use 4 vector compares when size is 4 * CHAR_PER_VEC or less.
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9. Use 8 vector compares when size is 8 * CHAR_PER_VEC or less.
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When possible the implementation tries to optimize for frontend in the
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following ways:
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Throughput:
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1. All code sections that fit are able to run optimally out of the
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LSD.
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2. All code sections that fit are able to run optimally out of the
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DSB
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3. Basic blocks are contained in minimum number of fetch blocks
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necessary.
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Latency:
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1. Logically connected basic blocks are put in the same
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cache-line.
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2. Logically connected basic blocks that do not fit in the same
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cache-line are put in adjacent lines. This can get beneficial
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L2 spatial prefetching and L1 next-line prefetching. */
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# include <sysdep.h>
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# ifndef MEMCMP
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# define MEMCMP __memcmp_evex_movbe
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# endif
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# ifndef VEC_SIZE
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# include "x86-evex256-vecs.h"
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# endif
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# ifdef USE_AS_WMEMCMP
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# define VMOVU_MASK vmovdqu32
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# define CHAR_SIZE 4
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# define VPCMP vpcmpd
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# define VPCMPEQ vpcmpeqd
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# define VPTEST vptestmd
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# define USE_WIDE_CHAR
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# else
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# define VMOVU_MASK vmovdqu8
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# define CHAR_SIZE 1
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# define VPCMP vpcmpub
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# define VPCMPEQ vpcmpeqb
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# define VPTEST vptestmb
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# endif
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# include "reg-macros.h"
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# define PAGE_SIZE 4096
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# define CHAR_PER_VEC (VEC_SIZE / CHAR_SIZE)
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/* Warning!
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wmemcmp has to use SIGNED comparison for elements.
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memcmp has to use UNSIGNED comparison for elements.
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*/
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.section SECTION(.text), "ax", @progbits
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/* Cache align memcmp entry. This allows for much more thorough
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frontend optimization. */
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ENTRY_P2ALIGN (MEMCMP, 6)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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movl %edx, %edx
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# endif
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cmp $CHAR_PER_VEC, %RDX_LP
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/* Fall through for [0, VEC_SIZE] as its the hottest. */
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ja L(more_1x_vec)
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/* Create mask of bytes that are guaranteed to be valid because
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of length (edx). Using masked movs allows us to skip checks
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for page crosses/zero size. */
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mov $-1, %VRAX
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bzhi %VRDX, %VRAX, %VRAX
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/* NB: A `jz` might be useful here. Page-faults that are
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invalidated by predicate execution (the evex mask) can be
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very slow. The expectation is this is not the norm so and
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"most" code will not regularly call 'memcmp' with length = 0
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and memory that is not wired up. */
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KMOV %VRAX, %k2
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/* Safe to load full ymm with mask. */
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VMOVU_MASK (%rsi), %VMM(2){%k2}{z}
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/* Slightly different method for VEC_SIZE == 64 to save a bit of
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code size. This allows us to fit L(return_vec_0) entirely in
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the first cache line. */
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# if VEC_SIZE == 64
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VPCMPEQ (%rdi), %VMM(2), %k1{%k2}
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KMOV %k1, %VRCX
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sub %VRCX, %VRAX
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# else
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VPCMP $4, (%rdi), %VMM(2), %k1{%k2}
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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# endif
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jnz L(return_vec_0)
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ret
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.p2align 4,, 11
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L(return_vec_0):
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WMEMCMP
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movl (%rdi, %rax, CHAR_SIZE), %ecx
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xorl %edx, %edx
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cmpl (%rsi, %rax, CHAR_SIZE), %ecx
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/* NB: no partial register stall here because xorl zero idiom
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above. */
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl (%rsi, %rax), %ecx
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# if VEC_SIZE == 64
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movb (%rdi, %rax), %al
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# else
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movzbl (%rdi, %rax), %eax
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# endif
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subl %ecx, %eax
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# endif
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ret
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.p2align 4,, 11
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L(more_1x_vec):
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/* From VEC to 2 * VEC. No branch when size == VEC_SIZE. */
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VMOVU (%rsi), %VMM(1)
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/* Use compare not equals to directly check for mismatch. */
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VPCMP $4, (%rdi), %VMM(1), %k1
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KMOV %k1, %VRAX
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/* NB: eax must be destination register if going to
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L(return_vec_[0,2]). For L(return_vec_3) destination
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register must be ecx. */
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test %VRAX, %VRAX
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jnz L(return_vec_0)
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cmpq $(CHAR_PER_VEC * 2), %rdx
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jbe L(last_1x_vec)
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/* Check second VEC no matter what. */
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VMOVU VEC_SIZE(%rsi), %VMM(2)
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VPCMP $4, VEC_SIZE(%rdi), %VMM(2), %k1
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_1)
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/* Less than 4 * VEC. */
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cmpq $(CHAR_PER_VEC * 4), %rdx
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jbe L(last_2x_vec)
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/* Check third and fourth VEC no matter what. */
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VMOVU (VEC_SIZE * 2)(%rsi), %VMM(3)
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VPCMP $4, (VEC_SIZE * 2)(%rdi), %VMM(3), %k1
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_2)
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VMOVU (VEC_SIZE * 3)(%rsi), %VMM(4)
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VPCMP $4, (VEC_SIZE * 3)(%rdi), %VMM(4), %k1
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KMOV %k1, %VRCX
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test %VRCX, %VRCX
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jnz L(return_vec_3)
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/* Go to 4x VEC loop. */
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cmpq $(CHAR_PER_VEC * 8), %rdx
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ja L(more_8x_vec)
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/* Handle remainder of size = 4 * VEC + 1 to 8 * VEC without any
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branches. */
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/* Load first two VEC from s2 before adjusting addresses. */
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VMOVU -(VEC_SIZE * 4)(%rsi, %rdx, CHAR_SIZE), %VMM(1)
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VMOVU -(VEC_SIZE * 3)(%rsi, %rdx, CHAR_SIZE), %VMM(2)
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leaq -(4 * VEC_SIZE)(%rdi, %rdx, CHAR_SIZE), %rdi
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leaq -(4 * VEC_SIZE)(%rsi, %rdx, CHAR_SIZE), %rsi
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/* Wait to load from s1 until addressed adjust due to
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unlamination of microfusion with complex address mode. */
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/* vpxor will be all 0s if s1 and s2 are equal. Otherwise it
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will have some 1s. */
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vpxorq (%rdi), %VMM(1), %VMM(1)
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vpxorq (VEC_SIZE)(%rdi), %VMM(2), %VMM(2)
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VMOVU (VEC_SIZE * 2)(%rsi), %VMM(3)
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vpxorq (VEC_SIZE * 2)(%rdi), %VMM(3), %VMM(3)
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VMOVU (VEC_SIZE * 3)(%rsi), %VMM(4)
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/* Ternary logic to xor (VEC_SIZE * 3)(%rdi) with VEC(4) while
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oring with VEC(1). Result is stored in VEC(4). */
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vpternlogd $0xde, (VEC_SIZE * 3)(%rdi), %VMM(1), %VMM(4)
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/* Or together VEC(2), VEC(3), and VEC(4) into VEC(4). */
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vpternlogd $0xfe, %VMM(2), %VMM(3), %VMM(4)
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/* Test VEC(4) against itself. Store any CHAR mismatches in k1.
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*/
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VPTEST %VMM(4), %VMM(4), %k1
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/* k1 must go to ecx for L(return_vec_0_1_2_3). */
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KMOV %k1, %VRCX
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test %VRCX, %VRCX
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jnz L(return_vec_0_1_2_3)
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/* NB: eax must be zero to reach here. */
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ret
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.p2align 4,, 9
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L(8x_end_return_vec_0_1_2_3):
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movq %rdx, %rdi
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L(8x_return_vec_0_1_2_3):
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/* L(loop_4x_vec) leaves result in `k1` for VEC_SIZE == 64. */
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# if VEC_SIZE == 64
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KMOV %k1, %VRCX
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# endif
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addq %rdi, %rsi
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L(return_vec_0_1_2_3):
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VPTEST %VMM(1), %VMM(1), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_0)
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VPTEST %VMM(2), %VMM(2), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_1)
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VPTEST %VMM(3), %VMM(3), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_2)
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.p2align 4,, 2
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L(return_vec_3):
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/* bsf saves 1 byte from tzcnt. This keep L(return_vec_3) in one
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fetch block and the entire L(*return_vec_0_1_2_3) in 1 cache
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line. */
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bsf %VRCX, %VRCX
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# ifdef USE_AS_WMEMCMP
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movl (VEC_SIZE * 3)(%rdi, %rcx, CHAR_SIZE), %eax
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xorl %edx, %edx
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cmpl (VEC_SIZE * 3)(%rsi, %rcx, CHAR_SIZE), %eax
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl (VEC_SIZE * 3)(%rdi, %rcx), %eax
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movzbl (VEC_SIZE * 3)(%rsi, %rcx), %ecx
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subl %ecx, %eax
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# endif
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ret
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.p2align 4,, 8
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L(return_vec_1):
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/* bsf saves 1 byte over tzcnt and keeps L(return_vec_1) in one
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fetch block. */
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WMEMCMP
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movl VEC_SIZE(%rdi, %rax, CHAR_SIZE), %ecx
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xorl %edx, %edx
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cmpl VEC_SIZE(%rsi, %rax, CHAR_SIZE), %ecx
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl VEC_SIZE(%rsi, %rax), %ecx
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movzbl VEC_SIZE(%rdi, %rax), %eax
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subl %ecx, %eax
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# endif
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ret
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.p2align 4,, 7
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L(return_vec_2):
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/* bsf saves 1 byte over tzcnt and keeps L(return_vec_2) in one
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fetch block. */
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WMEMCMP
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movl (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %ecx
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xorl %edx, %edx
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cmpl (VEC_SIZE * 2)(%rsi, %rax, CHAR_SIZE), %ecx
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl (VEC_SIZE * 2)(%rsi, %rax), %ecx
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movzbl (VEC_SIZE * 2)(%rdi, %rax), %eax
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subl %ecx, %eax
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# endif
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ret
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.p2align 4,, 8
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L(more_8x_vec):
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/* Set end of s1 in rdx. */
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leaq -(VEC_SIZE * 4)(%rdi, %rdx, CHAR_SIZE), %rdx
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/* rsi stores s2 - s1. This allows loop to only update one
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pointer. */
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subq %rdi, %rsi
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/* Align s1 pointer. */
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andq $-VEC_SIZE, %rdi
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/* Adjust because first 4x vec where check already. */
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subq $-(VEC_SIZE * 4), %rdi
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.p2align 4
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L(loop_4x_vec):
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VMOVU (%rsi, %rdi), %VMM(1)
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vpxorq (%rdi), %VMM(1), %VMM(1)
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VMOVU VEC_SIZE(%rsi, %rdi), %VMM(2)
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vpxorq VEC_SIZE(%rdi), %VMM(2), %VMM(2)
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VMOVU (VEC_SIZE * 2)(%rsi, %rdi), %VMM(3)
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vpxorq (VEC_SIZE * 2)(%rdi), %VMM(3), %VMM(3)
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VMOVU (VEC_SIZE * 3)(%rsi, %rdi), %VMM(4)
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vpternlogd $0xde, (VEC_SIZE * 3)(%rdi), %VMM(1), %VMM(4)
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vpternlogd $0xfe, %VMM(2), %VMM(3), %VMM(4)
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VPTEST %VMM(4), %VMM(4), %k1
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/* If VEC_SIZE == 64 just branch with KTEST. We have free port0
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space and it allows the loop to fit in 2x cache lines
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instead of 3. */
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# if VEC_SIZE == 64
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KTEST %k1, %k1
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# else
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KMOV %k1, %VRCX
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test %VRCX, %VRCX
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# endif
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jnz L(8x_return_vec_0_1_2_3)
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subq $-(VEC_SIZE * 4), %rdi
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cmpq %rdx, %rdi
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jb L(loop_4x_vec)
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subq %rdx, %rdi
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/* rdi has 4 * VEC_SIZE - remaining length. */
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cmpl $(VEC_SIZE * 3), %edi
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jge L(8x_last_1x_vec)
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/* Load regardless of branch. */
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VMOVU (VEC_SIZE * 2)(%rsi, %rdx), %VMM(3)
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/* Separate logic as we can only use testb for VEC_SIZE == 64.
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*/
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# if VEC_SIZE == 64
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testb %dil, %dil
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js L(8x_last_2x_vec)
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# else
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cmpl $(VEC_SIZE * 2), %edi
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jge L(8x_last_2x_vec)
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# endif
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vpxorq (VEC_SIZE * 2)(%rdx), %VMM(3), %VMM(3)
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VMOVU (%rsi, %rdx), %VMM(1)
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vpxorq (%rdx), %VMM(1), %VMM(1)
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VMOVU VEC_SIZE(%rsi, %rdx), %VMM(2)
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vpxorq VEC_SIZE(%rdx), %VMM(2), %VMM(2)
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VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %VMM(4)
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vpternlogd $0xde, (VEC_SIZE * 3)(%rdx), %VMM(1), %VMM(4)
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vpternlogd $0xfe, %VMM(2), %VMM(3), %VMM(4)
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VPTEST %VMM(4), %VMM(4), %k1
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/* L(8x_end_return_vec_0_1_2_3) expects bitmask to still be in
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`k1` if VEC_SIZE == 64. */
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# if VEC_SIZE == 64
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KTEST %k1, %k1
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# else
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KMOV %k1, %VRCX
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test %VRCX, %VRCX
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# endif
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jnz L(8x_end_return_vec_0_1_2_3)
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/* NB: eax must be zero to reach here. */
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ret
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/* Only entry is from L(more_8x_vec). */
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.p2align 4,, 6
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L(8x_last_2x_vec):
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VPCMP $4, (VEC_SIZE * 2)(%rdx), %VMM(3), %k1
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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jnz L(8x_return_vec_2)
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.p2align 4,, 5
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L(8x_last_1x_vec):
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VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %VMM(1)
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VPCMP $4, (VEC_SIZE * 3)(%rdx), %VMM(1), %k1
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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jnz L(8x_return_vec_3)
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ret
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/* Not ideally aligned (at offset +9 bytes in fetch block) but
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not aligning keeps it in the same cache line as
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L(8x_last_1x/2x_vec) so likely worth it. As well, saves code
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size. */
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.p2align 4,, 4
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L(8x_return_vec_2):
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subq $VEC_SIZE, %rdx
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L(8x_return_vec_3):
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WMEMCMP
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leaq (%rdx, %rax, CHAR_SIZE), %rax
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movl (VEC_SIZE * 3)(%rax), %ecx
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xorl %edx, %edx
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cmpl (VEC_SIZE * 3)(%rsi, %rax), %ecx
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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addq %rdx, %rax
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movzbl (VEC_SIZE * 3)(%rsi, %rax), %ecx
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movzbl (VEC_SIZE * 3)(%rax), %eax
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subl %ecx, %eax
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# endif
|
|
ret
|
|
|
|
.p2align 4,, 8
|
|
L(last_2x_vec):
|
|
/* Check second to last VEC. */
|
|
VMOVU -(VEC_SIZE * 2)(%rsi, %rdx, CHAR_SIZE), %VMM(1)
|
|
VPCMP $4, -(VEC_SIZE * 2)(%rdi, %rdx, CHAR_SIZE), %VMM(1), %k1
|
|
KMOV %k1, %VRAX
|
|
test %VRAX, %VRAX
|
|
jnz L(return_vec_1_end)
|
|
|
|
/* Check last VEC. */
|
|
.p2align 4,, 8
|
|
L(last_1x_vec):
|
|
VMOVU -(VEC_SIZE * 1)(%rsi, %rdx, CHAR_SIZE), %VMM(1)
|
|
VPCMP $4, -(VEC_SIZE * 1)(%rdi, %rdx, CHAR_SIZE), %VMM(1), %k1
|
|
KMOV %k1, %VRAX
|
|
test %VRAX, %VRAX
|
|
jnz L(return_vec_0_end)
|
|
ret
|
|
|
|
|
|
/* Don't fully align. Takes 2-fetch blocks either way and
|
|
aligning will cause code to spill into another cacheline.
|
|
*/
|
|
.p2align 4,, 3
|
|
L(return_vec_1_end):
|
|
/* Use bsf to save code size. This is necessary to have
|
|
L(one_or_less) fit in aligning bytes between. */
|
|
bsf %VRAX, %VRAX
|
|
addl %edx, %eax
|
|
# ifdef USE_AS_WMEMCMP
|
|
movl -(VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %ecx
|
|
xorl %edx, %edx
|
|
cmpl -(VEC_SIZE * 2)(%rsi, %rax, CHAR_SIZE), %ecx
|
|
setg %dl
|
|
leal -1(%rdx, %rdx), %eax
|
|
# else
|
|
movzbl -(VEC_SIZE * 2)(%rsi, %rax), %ecx
|
|
movzbl -(VEC_SIZE * 2)(%rdi, %rax), %eax
|
|
subl %ecx, %eax
|
|
# endif
|
|
ret
|
|
|
|
.p2align 4,, 2
|
|
/* Don't align. Takes 2-fetch blocks either way and aligning
|
|
will cause code to spill into another cacheline. */
|
|
L(return_vec_0_end):
|
|
bsf %VRAX, %VRAX
|
|
addl %edx, %eax
|
|
# ifdef USE_AS_WMEMCMP
|
|
movl -VEC_SIZE(%rdi, %rax, CHAR_SIZE), %ecx
|
|
xorl %edx, %edx
|
|
cmpl -VEC_SIZE(%rsi, %rax, CHAR_SIZE), %ecx
|
|
setg %dl
|
|
leal -1(%rdx, %rdx), %eax
|
|
# else
|
|
movzbl -VEC_SIZE(%rsi, %rax), %ecx
|
|
movzbl -VEC_SIZE(%rdi, %rax), %eax
|
|
subl %ecx, %eax
|
|
# endif
|
|
ret
|
|
/* evex256: 2-byte until next cache line. evex512: 46-bytes
|
|
until next cache line. */
|
|
END (MEMCMP)
|
|
#endif
|