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1ad8950a3e
glibc/sysdeps/powerpc/powerpc64/power8/fpu
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Adhemerval Zanella 1ad8950a3e PowerPC: llrint/llrintf POWER8 optimization 
This patch add a optimized llrint/llrintf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.
2014-02-27 12:58:33 -06:00
..
multiarch PowerPC: Adjust multiarch Implies for PowerPC64 2013-12-13 14:29:27 -05:00
Implies PowerPC: Adjust multiarch Implies for PowerPC64 2013-12-13 14:29:27 -05:00
s_finite.S PowerPC: Optimized finite/finitef for POWER8 2014-02-27 12:58:33 -06:00
s_finitef.S PowerPC: Optimized finite/finitef for POWER8 2014-02-27 12:58:33 -06:00
s_isinf.S PowerPC: Optimized isinf/isinff for POWER8 2014-02-27 12:58:33 -06:00
s_isinff.S PowerPC: Optimized isinf/isinff for POWER8 2014-02-27 12:58:33 -06:00
s_isnan.S PowerPC: Optimized isnan/isnanf for POWER8 2014-02-27 12:58:32 -06:00
s_isnanf.S PowerPC: Optimized isnan/isnanf for POWER8 2014-02-27 12:58:32 -06:00
s_llrint.S PowerPC: llrint/llrintf POWER8 optimization 2014-02-27 12:58:33 -06:00