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3dc426b642
Improve performance by handling another 16 bytes before entering the loop. Use ADDHN in the loop to avoid SHRN+FMOV when it terminates. Change final size computation to avoid increasing latency. On Neoverse V1 performance of the random strlen benchmark improves by 4.6%. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
109 lines
2.5 KiB
ArmAsm
109 lines
2.5 KiB
ArmAsm
/* Generic optimized strlen using SIMD.
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Copyright (C) 2012-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD.
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* MTE compatible.
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*/
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#ifndef STRLEN
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# define STRLEN __strlen
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#endif
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#define srcin x0
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#define result x0
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#define src x1
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#define synd x2
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#define tmp x3
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#define shift x4
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#define data q0
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#define vdata v0
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#define vhas_nul v1
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#define vend v2
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#define dend d2
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/* Core algorithm:
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Process the string in 16-byte aligned chunks. Compute a 64-bit mask with
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four bits per byte using the shrn instruction. A count trailing zeros then
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identifies the first zero byte. */
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ENTRY (STRLEN)
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PTR_ARG (0)
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bic src, srcin, 15
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ld1 {vdata.16b}, [src]
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cmeq vhas_nul.16b, vdata.16b, 0
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lsl shift, srcin, 2
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shrn vend.8b, vhas_nul.8h, 4 /* 128->64 */
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fmov synd, dend
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lsr synd, synd, shift
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cbz synd, L(next16)
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rbit synd, synd
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clz result, synd
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lsr result, result, 2
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ret
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L(next16):
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ldr data, [src, 16]
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cmeq vhas_nul.16b, vdata.16b, 0
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shrn vend.8b, vhas_nul.8h, 4 /* 128->64 */
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fmov synd, dend
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cbz synd, L(loop)
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add src, src, 16
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#ifndef __AARCH64EB__
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rbit synd, synd
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#endif
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sub result, src, srcin
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clz tmp, synd
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add result, result, tmp, lsr 2
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ret
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.p2align 5
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L(loop):
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ldr data, [src, 32]!
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cmeq vhas_nul.16b, vdata.16b, 0
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addhn vend.8b, vhas_nul.8h, vhas_nul.8h
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fmov synd, dend
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cbnz synd, L(loop_end)
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ldr data, [src, 16]
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cmeq vhas_nul.16b, vdata.16b, 0
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addhn vend.8b, vhas_nul.8h, vhas_nul.8h
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fmov synd, dend
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cbz synd, L(loop)
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add src, src, 16
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L(loop_end):
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sub result, shift, src, lsl 2 /* (srcin - src) << 2. */
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#ifndef __AARCH64EB__
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rbit synd, synd
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sub result, result, 3
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#endif
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clz tmp, synd
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sub result, tmp, result
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lsr result, result, 2
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ret
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END (STRLEN)
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weak_alias (STRLEN, strlen)
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libc_hidden_builtin_def (strlen)
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