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76a0b73e81
atomic_compare_and_exchange_bool_rel and catomic_compare_and_exchange_bool_rel are removed and replaced with the new C11-like atomic_compare_exchange_weak_release. The concurrent code in nscd/cache.c has not been reviewed yet, so this patch does not add detailed comments. * nscd/cache.c (cache_add): Use new C11-like atomic operation instead of atomic_compare_and_exchange_bool_rel. * nptl/pthread_mutex_unlock.c (__pthread_mutex_unlock_full): Likewise. * include/atomic.h (atomic_compare_and_exchange_bool_rel, catomic_compare_and_exchange_bool_rel): Remove. * sysdeps/aarch64/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise. * sysdeps/alpha/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise. * sysdeps/arm/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise. * sysdeps/mips/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise. * sysdeps/tile/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise.
267 lines
16 KiB
C
267 lines
16 KiB
C
/* Copyright (C) 2003-2016 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <stdint.h>
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#include <sysdep.h>
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typedef int8_t atomic8_t;
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typedef uint8_t uatomic8_t;
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typedef int_fast8_t atomic_fast8_t;
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typedef uint_fast8_t uatomic_fast8_t;
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typedef int32_t atomic32_t;
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typedef uint32_t uatomic32_t;
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typedef int_fast32_t atomic_fast32_t;
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typedef uint_fast32_t uatomic_fast32_t;
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typedef intptr_t atomicptr_t;
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typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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#define __HAVE_64B_ATOMICS 0
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#define USE_ATOMIC_COMPILER_BUILTINS 0
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/* Microblaze does not have byte and halfword forms of load and reserve and
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store conditional. So for microblaze we stub out the 8- and 16-bit forms. */
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#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
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(abort (), 0)
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#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
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(abort (), 0)
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#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" cmp %1, %0, %4;" \
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" bnei %1, 2f;" \
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" swx %5, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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"2:" \
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: "=&r" (__tmp), \
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"=&r" (test), \
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"=m" (*__memp) \
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: "r" (__memp), \
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"r" (oldval), \
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"r" (newval) \
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: "cc", "memory"); \
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__tmp; \
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})
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#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
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else \
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abort (); \
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__result; \
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})
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#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
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else \
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abort (); \
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__result; \
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})
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#define __arch_atomic_exchange_32_acq(mem, value) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %4, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" swx %3, %4, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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: "=&r" (__tmp), \
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"=&r" (test), \
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"=m" (*__memp) \
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: "r" (value), \
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"r" (__memp) \
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: "cc", "memory"); \
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__tmp; \
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})
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#define __arch_atomic_exchange_64_acq(mem, newval) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_exchange_acq(mem, value) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_atomic_exchange_32_acq (mem, value); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_atomic_exchange_64_acq (mem, value); \
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else \
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abort (); \
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__result; \
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})
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#define atomic_exchange_rel(mem, value) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_atomic_exchange_32_acq (mem, value); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_atomic_exchange_64_acq (mem, value); \
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else \
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abort (); \
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__result; \
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})
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#define __arch_atomic_exchange_and_add_32(mem, value) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %4, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" add %1, %3, %0;" \
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" swx %1, %4, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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: "=&r" (__tmp), \
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"=&r" (test), \
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"=m" (*__memp) \
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: "r" (value), \
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"r" (__memp) \
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: "cc", "memory"); \
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__tmp; \
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})
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#define __arch_atomic_exchange_and_add_64(mem, value) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_exchange_and_add(mem, value) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_atomic_exchange_and_add_32 (mem, value); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_atomic_exchange_and_add_64 (mem, value); \
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else \
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abort (); \
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__result; \
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})
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#define __arch_atomic_increment_val_32(mem) \
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({ \
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__typeof (*(mem)) __val; \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" addi %0, %0, 1;" \
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" swx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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: "=&r" (__val), \
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"=&r" (test), \
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"=m" (*mem) \
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: "r" (mem), \
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"m" (*mem) \
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: "cc", "memory"); \
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__val; \
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})
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#define __arch_atomic_increment_val_64(mem) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_increment_val(mem) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*(mem)) == 4) \
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__result = __arch_atomic_increment_val_32 (mem); \
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else if (sizeof (*(mem)) == 8) \
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__result = __arch_atomic_increment_val_64 (mem); \
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else \
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abort (); \
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__result; \
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})
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#define atomic_increment(mem) ({ atomic_increment_val (mem); (void) 0; })
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#define __arch_atomic_decrement_val_32(mem) \
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({ \
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__typeof (*(mem)) __val; \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" rsubi %0, %0, 1;" \
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" swx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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: "=&r" (__val), \
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"=&r" (test), \
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"=m" (*mem) \
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: "r" (mem), \
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"m" (*mem) \
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: "cc", "memory"); \
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__val; \
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})
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#define __arch_atomic_decrement_val_64(mem) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_decrement_val(mem) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*(mem)) == 4) \
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__result = __arch_atomic_decrement_val_32 (mem); \
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else if (sizeof (*(mem)) == 8) \
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__result = __arch_atomic_decrement_val_64 (mem); \
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else \
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abort (); \
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__result; \
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})
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#define atomic_decrement(mem) ({ atomic_decrement_val (mem); (void) 0; })
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