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b72ca61b71
Reserved bits in the Floating-Point Control and Status Register (FCSR) should not be implicitly cleared by fedisableexcept or feenableexcept, there is no reason to. Among these are the 8 condition codes and one of the two bits reserved for architecture implementers (bits #22 & #21). As to the latter, there is no reason to treat any of them as reserved either, they should be user controllable and settable via __fpu_control override as the user sees fit. For example in processors implemented by MIPS Technologies, such as the 5Kf or the 24Kf, these bits are used to change the treatment of denormalised operands and tiny results: bit #22 is Flush Override (FO) and bit #21 is Flush to Nearest (FN). They cause non-IEEE-compliant behaviour, but some programs may have a use for such modes of operation; the library should not obstruct such use just as it does not for the architectural Flush to Zero (FS) bit (bit #24). Therefore the change adjusts the reserved mask accordingly and also documents the distinction between bits 22:21 and 20:18. |
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| .. | ||
| e_sqrt.c | ||
| e_sqrtf.c | ||
| fclrexcpt.c | ||
| fedisblxcpt.c | ||
| feenablxcpt.c | ||
| fegetenv.c | ||
| fegetexcept.c | ||
| fegetround.c | ||
| feholdexcpt.c | ||
| fenv_libc.h | ||
| fesetenv.c | ||
| fesetround.c | ||
| feupdateenv.c | ||
| fgetexcptflg.c | ||
| fraiseexcpt.c | ||
| fsetexcptflg.c | ||
| ftestexcept.c | ||